IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0123463
(2005-05-04)
|
등록번호 |
US-7273767
(2007-09-25)
|
우선권정보 |
MY-PI 2004 5436(2004-12-31) |
발명자
/ 주소 |
- Ong,King Hoo
- Khor,Lily
- Liew,Boon Pek
- Thong,Kai Choh
|
출원인 / 주소 |
|
대리인 / 주소 |
Townsend and Townsend and Crew LLP
|
인용정보 |
피인용 횟수 :
16 인용 특허 :
27 |
초록
▼
A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a pl
A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface, prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of an integrated circuit die formed on the wafer without covering the plurality of bonding pads, curing the curable material and dicing the semiconductor wafer to separate the integrated circuit die from other integrated circuit die formed upon the wafer.
대표청구항
▼
What is claimed is: 1. A method of making packages for integrated circuit die, the method comprising: providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a
What is claimed is: 1. A method of making packages for integrated circuit die, the method comprising: providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface; prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of each integrated circuit die formed on the wafer without covering the plurality of bonding pads for the respective integrated circuit die; curing the curable material; dicing the semiconductor wafer to separate the plurality of integrated circuit die from each other; attaching at least some of the separated integrated circuit die to die pads of a lead frame strip; and applying an encapsulant material over the lead frame strip having the integrated circuit die attached; wherein the cured material extends above the encapsulant material. 2. The method of claim 1 wherein the lead frame strip is comprised of an outer frame and a plurality of horizontal and vertical connecting bars attached to the outer frame, wherein the horizontal and vertical connecting bars define a plurality of disposable inner frames arranged in a matrix pattern within the outer frame, each inner frame comprising a die pad at a center of the inner frame and integrally connected to the inner frame and a plurality of leads associated with the die pad and having an outer end integrally connected to the inner frame and wherein the method further comprises; electrically connecting each attached integrated circuit die to the first surface of each of the plurality of leads associated with its respective bonding pads. 3. The method of claim 2 wherein the encapsulant material is applied over the lead frame strip, such that for each of a plurality of integrated circuit die attached to a respective die pad within the lead frame strip, the encapsulant material covers the plurality of bond pads on the integrated circuit die, the electrical connections between the integrated circuit die and its associated plurality of leads and surrounds the cured material formed on the first surface of the integrated circuit die. 4. The method of claim 3 further comprising severing the die pad and the leads from the frame so as to detach the package from the frame. 5. The method of claim 3 wherein the curable material provides a transmission rate higher than or equal to 80% for wavelengths in the range of visible light. 6. The method of claim 1 wherein the curable material is applied to the wafer using a screen printing process. 7. The method of claim 1 wherein the curable material is applied to the wafer using jet dispensing techniques. 8. The method of claim 1 wherein the cured material extends above the encapsulant material by a height that is at least 10 percent of the height of the cured material. 9. The method of claim 1 wherein the cured material extends above the encapsulant material by a height that is between 10 to 50 percent of the height of the cured material. 10. The method of claim 2 wherein at least one of the bonding pads of each integrated circuit die is wire bonded to the first surface of at least one of the plurality of leads surrounding the integrated circuit die. 11. The method of claim 1 wherein the integrated circuit comprises an integrated circuit sensor chip. 12. The method of claim 1 wherein the curable material has a viscosity greater than about 60,000 centipoise. 13. The method of claim 1 further comprising planarizing an upper surface of the cured material and an upper surface of the encapsulant material. 14. A method of making packages for integrated circuit die, the method comprising: providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface; prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of each integrated circuit die formed on the wafer without covering the plurality of bonding pads for the respective integrated circuit die; curing the curable material; dicing the semiconductor wafer to separate the plurality of integrated circuit die from each other; after the dicing step, attaching at least some of the separated integrated circuit die to die pads of a lead frame strip; electrically connecting the integrated circuit die to at least one of a plurality of leads; applying an encapsulant material over the lead frame strip having the integrated circuit die attached; and after applying the encapsulant material, removing the cured material from the first surface of the integrated circuit die prior to severing the die pad and the leads from the frame. 15. A method of making a package for an integrated circuit die, the method comprising: providing a lead frame having a disposable metal frame, a metal die pad at a center of the frame and integrally connected to the frame and a plurality of metal leads each having an outer end integrally connected to the frame, wherein each of the metal frame, metal die pad and plurality of metal leads has a first surface and a second surface opposite the first surface; attaching an integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface to the metal die pad such that the second surface of the integrated circuit die faces the first surface of the metal die pad; electrically connecting the integrated circuit die to the first surface of each of the plurality of metal leads; applying an encapsulant material over the lead frame to cover the plurality of bond pads on the integrated circuit, the electrical connections between the integrated circuit die and the plurality of metal leads and surround the curable material; and severing the die pad and the leads from the frame so as to detach the package from the frame; wherein prior to applying the encapsulant material over the lead frame, a curable material is selectively applied over a portion of the first surface of the integrated circuit die without covering the plurality of bonding pads and the curable material is cured, and wherein after applying the encapsulant material the cured material extends above the encapsulant material. 16. The method of claim 15 farther comprising removing the cured material from the integrated circuit after the encapsulant material is applied over the lead frame. 17. The method of claim 16 wherein the cured material is mechanically removed from the integrated circuit. 18. The method of claim 16 wherein the cured material is chemically removed from the integrated circuit. 19. The method of claim 15 wherein the cured material is an optically transparent material that enables an unaided human eye to see the first surface of the integrated circuit. 20. The method of claim 19 wherein the curable material provides a transmission rate higher than or equal to 80% for wavelengths in the range of visible light. 21. A method of making a package for an integrated circuit die, the method comprising: providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface; prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of an integrated circuit die formed on the wafer without covering the plurality of bonding pads; curing the curable material; dicing the semiconductor wafer to separate the integrated circuit die from other integrated circuit die formed upon the wafer; providing a lead frame having a disposable metal frame, a metal die pad at a center of the frame and integrally connected to the frame and a plurality of metal leads each having an outer end integrally connected to the frame, wherein each of the metal frame, metal die pad and plurality of metal leads has a first surface and a second surface opposite the first surface; after the dicing step, attaching the integrated circuit die to the metal die pad such that the second surface of the integrated circuit die faces the first surface of the metal die pad; electrically connecting the integrated circuit die to the first surface of at least one of the plurality of metal leads; applying an encapsulant material over the lead frame to cover the plurality of bond pads on the integrated circuit, the electrical connections between the integrated circuit die and the plurality of metal leads and surround the cured material, wherein the cured material extends above the encapsulant material; and severing the die pad and the leads from the frame so as to detach the package from the frame. 22. The method of claim 21 wherein the step of attaching the integrated circuit die to the die pad comprises, for at least some die pads, attaching at least a second integrated circuit die to the die pad, and wherein the second integrated circuit die is subsequently covered with encapsulating material during the applying step. 23. The method of claim 22 wherein the second integrated circuit die does not include cured material over any portion of its surface. 24. A method of making packages for integrated circuit die, the method comprising: providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface; prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of each integrated circuit die formed on the wafer without covering the plurality of bonding pads for the respective integrated circuit die; curing the curable material; dicing the semiconductor wafer to separate the plurality of integrated circuit die from each other; after the dicing step, attaching at least some of the separated integrated circuit die to die pads of a lead frame strip; electrically connecting the integrated circuit die to at least one of a plurality of leads; applying an encapsulant material over the lead frame strip having the integrated circuit die attached; and after applying the encapsulant material, removing the cured material from the first surface of the integrated circuit die.
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