초록 ▼

Compiler flows are provided that can produce functionally equivalent field programmable gate arrays ("FPGAs") and structured application-specific integrated circuits ("structured ASICs"). The flows may include feeding back design transformations that are performed during either flow so that a later

Compiler flows are provided that can produce functionally equivalent field programmable gate arrays ("FPGAs") and structured application-specific integrated circuits ("structured ASICs"). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.

대표청구항 ▼

The invention claimed is: 1. A method of producing information for specifying a configuration of a structured ASIC that will be functionally equivalent to a programmed FPGA performing a user's logic design, the structured ASIC including multiple identical instances of a mask-programmable module for

The invention claimed is: 1. A method of producing information for specifying a configuration of a structured ASIC that will be functionally equivalent to a programmed FPGA performing a user's logic design, the structured ASIC including multiple identical instances of a mask-programmable module for use in implementing at least part of the user's logic design, the FPGA including multiple identical instances of a field-programmable module for use in implementing at least said part of the user's logic design, and each of the field-programmable modules having maximum logic capability that is greater than a maximum logic capability of one of the mask-programmable modules, the method comprising: synthesizing the user's logic design to produce a netlist that is suitable for implementing the user's logic design in the FPGA without specifying full place and route information for the FPGA implementation, the netlist including a synthesis of each of multiple portions of the user's logic design for implementation by a respective one instance of the field-programmable module; converting the netlist that results from the synthesizing to a modified netlist that is suitable for structured ASIC implementation of the user's logic design, the modified netlist including a conversion of the netlist for each of said portions of the user's logic design for implementation by a respective number of instances of the mask-programmable module, which number is different for at least some different ones of said portions of the user's logic design; performing a place and route operation on the modified netlist to produce a further synthesis adapted for placement on the structured ASIC; and further converting the further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC. 2. The method defined in claim 1 wherein the performing includes making a change in the modified netlist, and wherein the method further comprises: feeding the change back to modify the user's logic design. 3. The method defined in claim 2 wherein the change comprises: duplicating a register. 4. The method defined in claim 2 wherein the change comprises: shifting a register. 5. The method defined in claim 1 further comprising: performing a further place and route operation on the netlist that results from the synthesizing, the further place and route operation producing a still further synthesis adapted for placement on the FPGA. 6. The method defined in claim 5 wherein the performing a further place and route operation includes making a change in the netlist that results from the synthesizing, and wherein the method further comprises: feeding the change back to modify the user's logic design. 7. The method defined in claim 5 further comprising: comparing the further synthesis and the still further synthesis to test for functional equivalence. 8. A method of producing information for specifying a configuration of a structured ASIC that will be functionally equivalent to a programmed FPGA performing a user's logic design comprising: synthesizing the user's logic design for implementation in the FPGA; converting a synthesis that results from the synthesizing to a modified synthesis that is suitable for structured ASIC implementation; performing a place and route operation on the modified synthesis to produce a further synthesis adapted for placement on a structured ASIC; further converting the further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC; performing a further place and route operation on a synthesis that results from synthesizing the user's logic design for implementation in the FPGA, the further place and route operation producing a still further synthesis adapted for placement on the FPGA; and comparing the further synthesis and the still further synthesis to test for functional equivalence; wherein the comparing comprises: matching corresponding nodes in the further synthesis and the still further synthesis; constructing BDDs of logic between nodes, identified in the matching, in each of the further synthesis and the still further synthesis; and testing, for functional equivalence, corresponding BDDs in the further synthesis and the still further synthesis. 9. The method defined in claim 8 wherein the nodes include registers, non-logic block inputs and outputs, and logic cell outputs in the still further synthesis and corresponding logic outputs in the further synthesis. 10. The method defined in claim 7 wherein the comparing comprises: identifying corresponding non-logic blocks in the further synthesis and the still further synthesis; and testing, for similarity, functional parameter information for each of the corresponding non-logic blocks. 11. Machine-readable media encoded with machine-readable instructions for performing the method defined in claim 1. 12. A method of implementing a logic design in a structured ASIC, for which a functionally equivalent FPGA can be made, the structured ASIC including multiple identical instances of a mask-programmable module for use in implementing at least part of the logic design, the FPGA including multiple identical instances of a field-programmable module for use in implementing at least said part of the logic design, and each of the field-programmable modules having maximum logic capability that is greater than a maximum logic capability of one of the mask-programmable modules, the method comprising: producing an FPGA netlist of the logic design, which FPGA netlist does not include full place and route information for an FPGA implementation of the logic design, the FPGA netlist including a synthesis of each of multiple portions of the logic design for implementation by a respective one instance of the field-programmable module; converting the FPGA netlist to a structured ASIC netlist, the structured ASIC netlist including a conversion of the FPGA netlist for each of said portions of the logic design for implementation by a respective number of instances of the mask-programmable module, which number is different for at least some different ones of said portions of the logic design; performing a place and route operation on the structured ASIC netlist to produce a further synthesis adapted for placement on a structured ASIC; and converting the further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC.