초록 ▼

A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for

A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target, a FPGA, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing.

대표청구항 ▼

What is claimed is: 1. A method for synthesizing an embodiment in realizable devices from a behavioral specification of a design, the method comprising: adding to a design specification additional state information used in an embodiment as realizable devices, wherein the design specification compri

What is claimed is: 1. A method for synthesizing an embodiment in realizable devices from a behavioral specification of a design, the method comprising: adding to a design specification additional state information used in an embodiment as realizable devices, wherein the design specification comprises a plurality of types and subtypes representing a behavioral specification independent of an embodiment of tools implementing a synthesis process and independent of a specific design specification; specifying an embodiment of operators as realizable devices independent of the embodiment of tools implementing the synthesis process and independent of the specific design specification; representing an embodiment of persistent state instantiated from types and subtypes used in the specification and independent of the embodiment of tools implementing the synthesis process and independent of the specific design specification using a subprogram; and combining a behavioral specification with the steps of adding, specifying and representing, the combination yielding an embodiment or the behavioral specification as realizable devices. 2. The method from claim 1, further comprising: representing a mechanism by which devices which embody a specification continues to change a value of its state until a convergence criteria, defined independent of the specific design specification, is met. 3. The method from claim 1, further comprising: determining by the specification of convergence defined independent of the specific design specification if a convergent iteration is one which is initiated external to a specific embodiment device or specified subset of such devices within the embodiment or was during a subsequent iteration cycle. 4. The method from claim 1, further comprising: selecting with a synthesis tool among alternative augmentations of state wherein each alternative augmentation is defined independent of an embodiment of tools implementing a synthesis process and independent of the specific design specification so as to optimize characteristics of a resulting embodiment. 5. The method from claim 1, further comprising: selecting with a synthesis tool among alternative implementations of a type or subtype operator wherein each alternative implementation is defined independent of an embodiment of tools implementing a synthesis process and independent of the specific design specification so as to optimize characteristics of a resulting embodiment. 6. The method from claim 1, wherein a derivation from specification to embodiment is undertaken through successive application of alternative state augmentations and operators defined independent of tools implementation a synthesis process and independent of the specific design specification. 7. A method for verifying that an embodiment in electronic devices matches a behavioral specification, the method comprising: adding to a design specification additional state information used in an embodiment as realizable devices, wherein the design specification comprises a plurality of types and subtypes representing a behavioral specification independent of an embodiment of tools implementing a verification process and independent of a specific design specification; specifying an embodiment of operators as realizable devices independent of the embodiment of tools implementing the verification process and independent of the specific design specification; representing an embodiment of persistent state instantiated from types and subtypes used in the specification and independent of the embodiment of tools implementing the verification process using a subprogram; and combining a behavioral specification with the steps or adding, specifying and representing, the combination yielding a simulation predicting behavior of a behavioral specification. 8. The method From claim 7, further comprising: representing a mechanism by which devices which embody a specification continues to change a value of its state until a convergence criteria, defined independent of the specific design specification, is met. 9. The method from claim 7, further comprising: determining by a specification of convergence defined independent of the specific design specification if a convergent iteration is one which is initiated external to a specific embodiment device or specified subset of such devices within the embodiment or was during a subsequent iteration cycle. 10. The method from claim 7, wherein a derivation from specification to embodiment is undertaken through successive application or alternative state augmentations and operators defined independent of tools implementing a verification process and independent of the specific design specification.