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Methods and apparatus for compiling instructions for a data processor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/44
출원번호 US-0330632 (2002-12-26)
등록번호 US-7278137 (2007-10-02)
발명자 / 주소
  • Fuhler,Richard A.
  • Pennello,Thomas J.
  • Jalkut,Michael Lee
  • Warnes,Peter
출원인 / 주소
  • ARC International
대리인 / 주소
    Gazdzinski & Associates
인용정보 피인용 횟수 : 28  인용 특허 : 69

초록

Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approach

대표청구항

We claim: 1. A method of compiling an instruction set for a digital processor having variable length instructions, comprising: generating at least one instruction; canonicalizing the address calculation associated with said at least one instruction in at least first and second instances, said first

이 특허에 인용된 특허 (69)

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  2. Bernhard, Egger; Ryu, Soo-jung; Yoo, Dong-hoon; Park, Il-hyun, Apparatus and method for providing instruction for heterogeneous processor.
  3. Goodwin, David William; Maydan, Dror; Chen, Ding-Kai; Petkov, Darin Stamenov; Tjiang, Steven Weng-Kiang; Tu, Peng; Rowen, Christopher, Automatic instruction set architecture generation.
  4. Tarditi, Jr., David Read; Harris, Timothy Lawrence; Plesko, Mark Ronald; Shinnar, Avraham E., Compiler support for optimizing decomposed software transactional memory operations.
  5. Porras, Victor Leonel Hernandez; Hoover, Roger Scott; Lattner, Christopher Arthur; Christopher, Eric Marshall, Deferred constant pool generation.
  6. Gal, Andreas Imre; Franz, Michael, Dynamic incremental compiler and method.
  7. Harris, Timothy Lawrence, Efficient placement of software transactional memory operations around procedure calls.
  8. Gafter, Neal M.; Torgersen, Mads; Meijer, Henricus Johannes Maria; Gustafsson, Niklas, Efficient resumption of co-routines on a linear stack.
  9. Kang, Sangyeol; Miclea, Ovidiu Cristian; Verrall, Stephen Michael, Hierarchical synthesis of computer machine instructions.
  10. Harris, Timothy Lawrence, Implementing strong atomicity in software transactional memory.
  11. Meijer, Henricus Johannes Maria; Schach, David; Aharoni, Avner Y.; Schulte, Wolfram, Interaction with nested and non-nested streams.
  12. Cheriton, David R., Interpreter-based program language translator using embedded interpreter types and variables.
  13. Yang, Kun Hua; Wang, Shao Chung; Lee, Jenq Kuen, Method and apparatus for code size reduction.
  14. Ferguson, Jonathan, Method and apparatus for implementing decode operations in a data processor.
  15. Warnes, Peter, Method and apparatus for processor code optimization using code compression.
  16. Chen, Gang, Method and apparatus for reducing instruction dependencies in extended SSA form instructions.
  17. Fuhler, Richard A.; Pennello, Thomas J.; Jalkut, Michael Lee; Warnes, Peter, Methods and apparatus for compiling instructions for a data processor.
  18. Laksono, Indra; Yang, Kai; Wang, Hongri; Liu, Dong; Zhao, Xu Gang; Young, Eric; Hong, Edward, Multi-format video decoder with vector processing instructions and methods for use therewith.
  19. Makarov, Vladimir, Performing register allocation of program variables based on priority spills and assignments.
  20. Inoue, Hiroshi, Reducing overhead in loading constants.
  21. Tarditi, Jr., David Read; Plesko, Mark Ronald, Reducing unnecessary software transactional memory operations on newly-allocated data.
  22. Shinnar, Avraham E.; Harris, Timothy Lawrence; Tarditi, Jr., David Read; Plesko, Mark Ronald, Removal of unnecessary read-to-update upgrades in software transactional memory.
  23. Chinchalkar, Avinash Srikrishna; Ramajeyam, Balamurugan; Srinivasan, Muthulakshmi Pearl; Warrier, Suresh Eswara, Selective execution of trace mechanisms for applications having different bit structures.
  24. Iwasaki, Mitsuru, System and method generating object code.
  25. Hill, Gerhard, Systems and methods for assigning hosts in response to a data query.
  26. Hill, Gerhard, Systems and methods for assigning hosts in response to a data query.
  27. Schmidt, David; Abels, Timothy, Task generation runtime engine.
  28. Sule, Dineel Diwakar; Stotzer, Eric J.; Hahn, Todd T., Tiered register allocation.
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