IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
US-0330632
(2002-12-26)
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등록번호 |
US-7278137
(2007-10-02)
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발명자
/ 주소 |
- Fuhler,Richard A.
- Pennello,Thomas J.
- Jalkut,Michael Lee
- Warnes,Peter
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
28 인용 특허 :
69 |
초록
▼
Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approach
Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the "regular" 32-bit instruction addressing modes, and the second for the "compressed" 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.
대표청구항
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We claim: 1. A method of compiling an instruction set for a digital processor having variable length instructions, comprising: generating at least one instruction; canonicalizing the address calculation associated with said at least one instruction in at least first and second instances, said first
We claim: 1. A method of compiling an instruction set for a digital processor having variable length instructions, comprising: generating at least one instruction; canonicalizing the address calculation associated with said at least one instruction in at least first and second instances, said first instance comprising the address calculation relating to a first instruction word length, and said second instance relating to a second instruction word length, said second length being smaller than said first length; and selecting one of said first or second instances based on producing the smallest instruction set. 2. The method of claim 1, wherein said first and second instances of address calculation comprise respective first and second effective address operands (EAs), said first and second operands comprising a plurality of sources to said at least one instruction. 3. The method of claim 1, further comprising reducing the number of function calls occurring within said instruction set. 4. The method of claim 3, wherein said act of reducing comprises selectively utilizing indirect calls within said instruction set. 5. The method of claim 4, wherein said selectively utilizing indirect calls further comprises placing the addresses associated with said indirect calls in at least one constant pool. 6. A method selecting an address operand for use with an instruction in an instruction set of a digital processor, comprising: canonicalizing an address calculation associated with said instruction according to a first word form; canonicalizing an address calculation associated with said instruction according to a second word form; and selecting one of said first and second word forms for use with said instruction based at least in part on producing the smallest instruction set. 7. The method of claim 6, wherein said act of selecting comprises selecting based at least in part on which of said first or second word forms will generate the least number of instructions in an instruction set for said processor. 8. The method of claim 7, wherein said act of canonicalizing according to a first word form comprises canonicalizing to a word form adapted for a first addressing mode within said processor, and said act of canonicalizing according to a second word form comprises canonicalizing to a word form adapted for a second addressing mode. 9. The method of claim 8, wherein said first and second modes comprise 32-bit and 16-bit addressing modes, respectively. 10. The method of claim 7, further comprising optimizing said instruction set to reduce the number of instructions. 11. A method of minimizing the size of an instruction set of a data processor, the method comprising: providing a plurality of instructions adapted to utilize at least first and second addressing modes; performing address calculations in at least a first word form for said first addressing mode and a second word form for said second addressing mode; determining which of said first or second word forms will generate the fewest number of instructions in said set; and selecting said first or second word form for said plurality of instructions based at least in part on said act of determining. 12. The method of claim 11, further comprising optimizing said instruction set prior to said act of determining. 13. The method of claim 11, wherein said act of performing address calculations comprises canonicalization. 14. A digital processor having a multistage pipeline, storage device, and an instruction set stored at least partly in said storage device, said instruction set being generated using the method comprising: performing address calculations associated with a plurality of instructions in said set in a plurality of word forms, said plurality comprising at least a first word form for first addressing modes, and a second word form for second addressing modes; determining which of said first or second word forms will produce the smallest instruction set; selecting said first or second word form based at least in part on said act of determining; and compiling said instruction set based at least in part on said act of selecting. 15. The processor of claim 14, wherein said processor comprises a RISC processor core, and said first and second addressing modes comprise 32-bit and 16-bit modes. 16. The processor of claim 15, wherein said instruction set comprises a plurality of base instructions and at least one extension instruction. 17. The processor of claim 16, wherein said plurality of instructions comprises at least one extension instruction. 18. A method of generating an instruction set for a digital processor having a variable-length ISA, comprising: providing at least two word forms of each of a plurality of instructions; reading each of said at least two word forms for at least one of said plurality of instructions; determining which of said at least two word forms associated with each at least one instruction is smaller; and selecting one of said word forms based on producing the smallest instruction set. 19. A method of generating a size-optimized instruction set for a user-configurable RISC processor having a variable-length ISA with 32-bit and 16-bit instruction formats, comprising: providing a plurality of instructions capable of utilizing either of said word formats; reading each of said word formats for each of said plurality of instructions; determining, for each of said plurality of instructions, which of said two word formats produces a smaller instruction size; and selecting, for at least a portion of said plurality of instructions, the word format which produces the smaller size. 20. For use in an extended and user-configurable digital processor having an instruction set comprising a plurality of variable length instructions, a method of compiling an instruction set comprising: generating at least one instruction, said at least one instruction comprising at least one instruction forming at least part of either a base case processor instruction population or an extension instruction population; canonicalizing the address calculation associated with said at least one instruction in at least first and second instances, said first instance comprising the address calculation relating to a first instruction word length, and said second instance relating to a second instruction word length, said second length being smaller than said first length; and selecting one of said first or second instances based on producing the smallest instruction set. 21. The method of claim 20, wherein said first word length comprises 32-bits, and said second word length comprises 16-bits. 22. The method of claim 21, wherein said processor is configured to switch between said 32-bit instruction word lengths and 16-bit instruction word lengths during operation without requiring a processor mode switch. 23. The method of claim 22, wherein said act of selecting comprises using a Single Static Assignment (SSA) process. 24. A method selecting an address operand for use with a functional instruction in an instruction set of a reduced instruction set (RISC) digital processor, said processor comprising a mixed-length instruction set architecture (ISA) having at least a plurality of 32-bit instruction words, and at least a plurality of 16-bit instruction words, the processor and ISA allowing for free-form mixing of said 32-bit and 16-bit instruction words without a processor mode switch, the method comprising: canonicalizing an address calculation associated with said functional instruction according to a 32-bit word form; canonicalizing an address calculation associated with said instruction according to a 16-bit word form; and selecting one of said 32-bit or 16-bit word forms for use with said functional instruction based at least in part on which of said 32-bit or 16-bit word forms will generate the least number of instructions in the instruction set.
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