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특허 상세정보

Power managed busses and arbitration

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-013/18    G06F-013/16   
미국특허분류(USC) 713/322; 710/309
출원번호 US-0809970 (2004-03-26)
등록번호 US-7281148 (2007-10-09)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 15  인용 특허 : 27
초록

A variable speed bus has its frequency adjusted based upon bandwidth requirements of active units coupled to a variable speed bus. As units coupled to the bus are stopped, bandwidth requirements are lowered and the bus frequency is reduced in response to the lowered bandwidth requirements. An arbiter selects an appropriate arbitration configuration based on which units are active and which are stopped. The arbitration configuration is adjusted to ensure that the bandwidth requirements of the active units are sustained despite the reduced clock frequency...

대표
청구항

What is claimed is: 1. An apparatus, comprising: a variable speed bus; a first unit coupled to the variable speed bus; a second unit coupled to the variable speed bus; and an arbitration and bus clock control unit to adjust the variable speed bus frequency depending on the bandwidth requirements of the first and second units, the arbitration and bus clock control unit to monitor which of the first and second units are active and to select an appropriate arbitration configuration depending on which of the first and second units are active, wherein the ar...

이 특허에 인용된 특허 (27)

  1. Voit, Paul J.. Apparatus and method for automatically selecting an appropriate signal from a plurality of signals, based on the configuration of a peripheral installed within a computing device. USP2003016510473.
  2. Finnie, Donald; Strathmeyer, Carl R.. Automatic call distribution with computer telephony interface enablement. USP2005076920216.
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  4. Fung Henry T. (San Jose CA) Tsang Siu K. (San Jose CA) Mitchell Phillip M. (Milpitas CA) Farquhar Norman P. (San Jose CA). Computer having a single bus supporting multiple bus architectures operating with different bus parameters. USP1997055630163.
  5. Baker Roy S. (Rockford IL) Nuechterlein Paul E. (Rockford IL). Converter enhanced variable frequency power bus architecture. USP1997055627744.
  6. Wolford Robert Russell. Data processing system and method for dynamically setting bus clock frequency in response to a number of loads. USP2001026185692.
  7. Holland, John; Ranford, Paul; Robson, Peter. Fault tolerant voice processing system. USP2003046556672.
  8. Wagner Larry ; Wu Carol. Filtering audio signals from a combined microphone/speaker earpiece. USP1999095949891.
  9. Arimilli Ravi K. (Round Rock TX) Dhawan Sudhir (Austin TX) Lerom George A. (Austin TX) Nicholson James O. (Austin TX) Siegel David W. (Austin TX). High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of. USP1993085237676.
  10. Shires, Glen E.. Matching routed call to agent workstation. USP2004096792102.
  11. Oprescu Florin (Sunnyvale CA) Teener Michael D. (Santa Cruz CA). Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface. USP1996045509126.
  12. Oprescu Florin (Sunnyvale CA) Van Brunt Roger (San Francisco CA). Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independe. USP1996095559967.
  13. Young Bruce. Method and apparatus for dynamically adjusting the clock speed of a bus depending on bus activity. USP2000066079022.
  14. Crook, John. Method and system for configuring among call processing applications in a call processing system. USP2003116642942.
  15. John Holland NZ; Paul Ranford NZ; Peter Robson NZ; Neal Oliver. Multiple platform voice processing system with optimized resource allocation. USP2002076418201.
  16. Nishtala Satyanarayana (Cupertino CA) Ebrahim Zahir (Mountain View CA) Van Loo William C. (Palo Alto CA) Loewenstein Paul (Palo Alto CA) Lee Sue K. (San Mateo CA) Coffin III Louis F. (San Jose CA). Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multi. USP1996125581729.
  17. Culbert, Michael F.; Howard, Brian D.. Power managed graphics controller. USP2004116820209.
  18. Iwazaki Yasuo,JPX. Power-saving clock control apparatus and method. USP2000066073244.
  19. Barnaby Michael J. ; Mammen Abe. Priority encoding and decoding for memory architecture. USP1999126006303.
  20. Harrison Robert W. (18 Westfield Park Cortland NY 13045) Whitney Alan (227 Prospect Hill Rd. Horseheads NY 14845). Remote speaker for surround-sound applications. USP1997095666422.
  21. Ramachandran, Navindra. Software call control agent. USP2005026853720.
  22. O\Brien Rita M. (Austin TX). System and method for controlling a peripheral bus clock signal during a reduced power mode. USP1997055628019.
  23. Martina K. Hartmeier. System and method for providing call statistics in real time. USP2002066404883.
  24. David M. Olson ; Ashley H. Gorakhpurwalla. System for incorporating multiple expansion slots in a variable speed peripheral bus. USP2002116484222.
  25. Larson James A ; Boss Scott ; Veeramoney Murali ; Rosenweig Mike ; Hurwitz Roger ; Colville Scott ; Raman T. V.. Telephone access system for accessing a computer through a telephone handset. USP1998105825854.
  26. Wymore, Ben S.; Genly, Christopher H.; Hicks, David G.. Using speech to select a position in a program. USP2004056741791.
  27. Kelley Richard Allen ; Neal Danny Marvin ; Nicholson James Otto ; Thurber Steven Mark. Variable slot configuration for multi-speed bus. USP2000106134621.

이 특허를 인용한 특허 피인용횟수: 15

  1. Munguia, Peter R.. Apparatus for adjusting a clock frequency of a variable speed bus. USP2009107606960.
  2. Stedman, Roy W.; Sultenfuss, Andrew T.; Loadman, David. Enabling access to peripheral resources at a processor. USP2013068463957.
  3. Belt, Steven L.; Sultenfuss, Andrew T.. Information handling system with processing system, low-power processing system and shared resources. USP2012098271817.
  4. Belt, Steven L.; Sultenfuss, Andrew T.. Information handling system with processing system, low-power processing system and shared resources. USP2011108037333.
  5. Belt, Steven L.; Sultenfuss, Andrew T.. Information handling system with processing system, low-power processing system and shared resources. USP2014088799695.
  6. Hou, Ping-Cheng; Lu, Cheng-Yu; Shih, Chieh-Wen; Wu, Jen-Shi; Chen, Chung-Ching. Multi-core electronic system having a rate adjustment module for setting a minimum transmission rate that is capable for meeting the total bandwidth requirement to a shared data transmission interface. USP2014098850248.
  7. Sultenfuss, Andrew T.. Power control for information handling system having shared resources. USP2011118065540.
  8. Sultenfuss, Andrew T.. Power control for information handling system having shared resources. USP2013118583953.
  9. Chrysanthakopoulos, Georgios; Gray, Donald M.. Resource management via periodic distributed time. USP2014118881233.
  10. Stedman, Roy W.; Sultenfuss, Andrew T.; Loadman, David. Security module and method within an information handling system. USP2014108863268.
  11. Sultenfuss, Andrew T.; Loadman, David. System and method of polling with an information handling system. USP20181210148787.
  12. Stedman, Roy W.; Sultenfuss, Andrew T.. System and method of utilizing resources within an information handling system. USP2013028370673.
  13. Stedman, Roy W.; Sultenfuss, Andrew T.; Loadman, David. System and method of utilizing resources within an information handling system. USP2014078769328.
  14. Utz, James R.; Sultenfuss, Andrew T.; Loadman, David. System, module and method of enabling a video interface within a limited resource enabled information handling system. USP2012038134565.
  15. Utz, James R.; Sultenfuss, Andrew T.; Loadman, David C.. System, module, and method of enabling a video interface within a limited resource enabled information handling system. USP2013088520014.