Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/44
H01L-021/02
출원번호
US-0032975
(2005-01-10)
등록번호
US-7282433
(2007-10-16)
발명자
/ 주소
Tang,Sanh D.
Tuttle,Mark E.
Cook,Keith R.
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Perkins Coie LLP
인용정보
피인용 횟수 :
11인용 특허 :
14
초록▼
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electri
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
대표청구항▼
We claim: 1. A method of forming bump sites on bond-pads in the manufacturing of microelectronic devices, comprising: providing a microelectronic workpiece having a plurality of dies, wherein individual dies include integrated circuitry and bond-pads electrically coupled to the integrated circuitry
We claim: 1. A method of forming bump sites on bond-pads in the manufacturing of microelectronic devices, comprising: providing a microelectronic workpiece having a plurality of dies, wherein individual dies include integrated circuitry and bond-pads electrically coupled to the integrated circuitry; forming a passivation structure on the workpiece, wherein forming the passivation structure comprises depositing a first dielectric over the workpiece, a second dielectric layer onto the first dielectric layer, and a photo-active third dielectric layer onto the second dielectric layer; creating openings in the passivation structure to at least partially expose the bond-pads, wherein creating openings in the passivation structure comprises developing the photo-active third dielectric layer to form a mask having holes aligned with the bond-pads, etching using the mask through the first and second dielectric layers to form openings having sidewalls projecting from corresponding bond-pads, and forming shoulders in the openings that extend transversely to the sidewalls; depositing an intermediate layer onto the bond-pads and the passivation structure; depositing an external metal layer over the passivation structure and the bond-pads, wherein depositing an external metal layer comprises depositing an aluminum layer onto the intermediate layer; and planarizing the workpiece by placing the workpiece against a planarizing medium and moving the workpiece and/or the planarizing medium relative to each other in a manner that removes portions of the external metal layer from the passivation structure, wherein planarizing the workpiece comprises chemical-mechanical planarization of portions of the intermediate layer and the external metal layer from a top surface of the third dielectric layer to leave self-aligned caps over the bond-pads. 2. The method of claim 1 wherein depositing the metal layer comprises depositing the metal layer to a thickness less than a thickness of the passivation structure such that the metal layer does not completely fill the openings in the passivation structure before planarizing the workpiece. 3. The method of claim 1 wherein the bond-pads are copper and the intermediate layer is a barrier layer that inhibits copper from diffusing into the external metal layer. 4. The method of claim 1 wherein the third dielectric layer comprises PBO. 5. The method of claim 1 wherein the intermediate layer is a barrier layer comprising tantalum, titanium and/or tungsten. 6. The method of claim 1 wherein the method further comprises depositing a sacrificial material onto the metal layer before planarizing the workpiece, and stripping remaining portions of the sacrificial material after planarizing the workpiece. 7. The method of claim 1 wherein the passivation structure has a thickness configured to prevent dishing into portions of the intermediate layer over the bond-pads during the planarizing stage. 8. The method of claim 7 wherein the third dielectric layer has a thickness of approximately 4 μm. 9. A method of forming bump sites on bond-pads in the manufacturing of microelectronic devices, comprising: providing a microelectronic workpiece having a plurality of dies, wherein individual dies include integrated circuitry and bond-pads electrically coupled to the integrated circuitry; constructing a dielectric structure such that the dielectric structure has openings aligned with corresponding bond-pads and the openings have (a) sidewalls arranged to at least partially expose the bond-pads and (b) shoulders projecting transversely relative to the sidewalls, wherein constructing the dielectric structure comprises forming a passivation structure by depositing a first dielectric layer over the workpiece, depositing a second dielectric layer onto the first dielectric layer, depositing a photo-active third dielectric layer onto the second dielectric layer, developing the third dielectric layer to form a mask having holes aligned with the bond-pads, and etching using the mask through the first and second dielectric layers to form the openings, wherein the sidewalls of the openings extend through the first, second and third dielectric layers and project from the bond-pads; depositing a metal layer over the dielectric structure and the bond-pads, wherein metal layer has steps seated with the shoulders in the openings; and removing portions of the metal layer from upper portions of the dielectric structure to form self-aligned caps over the bond-pads by placing the workpiece against a planarizing medium and moving the workpiece and/or the planarizing medium relative to each other. 10. The method of claim 9 further comprising forming the shoulders by eroding the third dielectric layer such that an upper surface of the second dielectric layer projects laterally inward into the openings beyond a lower surface of the third dielectric layer. 11. The method of claim 9 wherein the third dielectric layer comprises PBO. 12. The method of claim 9 wherein the third dielectric layer has a thickness configured to prevent dishing through the portions of the metal layer over the bond-pads during the planarization stage. 13. The method of claim 9, further comprising (a) depositing an intermediate layer onto the dielectric structure before depositing the metal layer, and (b) removing portions of both the metal layer and the intermediate layer from the upper portions of the dielectric structure by planarizing the workpiece to form the self-aligned caps having a discrete portion of the barrier layer and a discrete portion of the metal layer. 14. The method of claim 13 wherein the bond-pads comprise one or more of copper, silver and gold. 15. The method of claim 9 wherein removing portions of the metal layer from upper portions of the dielectric structure comprises exposing a surface of the third dielectric layer. 16. A method of forming bump sites on copper bond-pads in the manufacturing of microelectronic devices, comprising: providing a microelectronic workpiece having a plurality of dies, wherein individual dies include integrated circuitry and copper bond-pads electrically coupled to the integrated circuitry; constructing a dielectric structure on the workpiece such that the dielectric structure has openings arranged to at least partially expose individual copper bond-pads, wherein constructing the dielectric structure comprises forming a passivation structure by depositing a first dielectric layer over the workpiece, depositing a second dielectric layer onto the first dielectric layer, depositing a photo-active third dielectric layer onto the second dielectric layer, developing the third dielectric layer to form a mask having holes aligned with the bond-pads, and etching using the mask through the first and second dielectric layers to form the openings, wherein sidewalls of the openings extend through the first, second and third dielectric layers and project from the bond-pads; forming a barrier layer on the dielectric structure and the exposed portions of the bond-pads; depositing an aluminum layer onto the barrier layer; coating the aluminum layer with a sacrificial material; removing portions of the sacrificial material, the aluminum layer, and the barrier layer from upper portions of the dielectric structure by placing the workpiece against a planarizing medium and moving the workpiece and/or the planarizing medium relative to each other; and removing remaining portions of the sacrificial material from the workpiece. 17. The method of claim 16 wherein removing portions of the sacrificial material, the aluminum layer, and the barrier layer comprises exposing a surface of the third dielectric layer. 18. A method of forming bump sites on bond-pads in the manufacturing of microelectronic devices, comprising: providing a microelectronic workpiece having a plurality of dies, wherein individual dies include integrated circuitry and bond-pads electrically coupled to the integrated circuitry; constructing a dielectric structure on the workpiece such that the dielectric structure has openings aligned with corresponding bond-pads, wherein constructing the dielectric structure comprises forming a passivation structure by depositing a first dielectric layer over the workpiece, depositing a second dielectric layer onto the first dielectric layer, depositing a photo-active third dielectric layer onto the second dielectric layer, developing the third dielectric layer to form a mask having holes aligned with the bond-pads, and etching using the mask through the first and second dielectric layers to form the openings, wherein the openings have sidewalls that extend through the first, second and third dielectric layers and project from the bond-pads; depositing a conductive cap layer over the dielectric structure and the bond-pads; removing portions of the cap layer from the workpiece without forming a mask over the cap layer to form caps comprising discrete portions of the cap layer that are self-aligned with corresponding copper bond-pads. 19. The method of claim 18 further comprising forming shoulders in the openings by eroding the third dielectric layer such that an upper surface of the second dielectric layer projects laterally inward into the openings beyond a lower surface of the third dielectric layer. 20. The method of claim 19, further comprising forming a conductive barrier layer over the dielectric structure by depositing a diffusion barrier material onto the bond-pads and the sidewalls of the openings, and wherein: depositing a cap layer comprises depositing an aluminum layer onto the diffusion barrier material, wherein the aluminum layer and the diffusion barrier material have steps seated with the shoulders in the openings; and removing the portions of the cap layer and the barrier layer without forming a mask comprises chemical-mechanical planarization of portions of the aluminum layer and the diffusion barrier material from a top surface of the third dielectric layer to leave self-aligned caps over the bond-pads. 21. The method of claim 18 wherein removing the portions of the cap layer without forming a mask comprises planarizing the workpiece using a chemical-mechanical planarization process. 22. The method of claim 21 wherein removing the portions of the cap layer without forming a mask further comprises exposing a surface of the third dielectric layer. 23. The method of claim 18 wherein the method further comprises forming a conductive barrier layer over the dielectric structure by depositing a diffusion barrier material onto the bond-pads and the sidewalls of the openings, depositing a sacrificial material onto the cap layer before planarizing the workpiece, and stripping remaining portions of the sacrificial material after planarizing the workpiece, and wherein: depositing a cap layer comprises depositing an aluminum layer onto the diffusion barrier material; and removing the portions of the cap layer and the barrier layer without forming a mask comprises chemical-mechanical planarization of portions of the aluminum layer and the diffusion barrier material from a top surface of the second dielectric layer to leave self-aligned caps over the bond-pads before stripping the remaining portions of sacrificial material from the workpiece.
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