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Semiconductor devices at least partially covered by a composite coating including particles dispersed through photopolymer material 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/28
  • H01L-023/29
  • H01L-023/02
  • H01L-023/053
  • H01L-023/14
  • H01L-023/12
출원번호 US-0516422 (2006-09-05)
등록번호 US-7282806 (2007-10-16)
발명자 / 주소
  • Hembree,David R.
  • Farnworth,Warren M.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 5  인용 특허 : 87

초록

Devices include at least one semiconductor die including at least one surface that is at least partially covered by a photopolymer material. The photopolymer material includes a plurality of discrete particles dispersed through a polymerized matrix. In some embodiments, the photopolymer material may

대표청구항

What is claimed is: 1. A device comprising at least one semiconductor die including at least one surface at least partially covered by a first cured photopolymer material comprising a plurality of discrete particles dispersed through a polymerized matrix. 2. The device of claim 1, wherein the fir

이 특허에 인용된 특허 (87)

  1. Gothait Hanan,ILX, Apparatus and method for three dimensional model printing.
  2. Derderian, James M., Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods.
  3. Akram, Salman; Ahmad, Syed Sajid, Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same.
  4. Bruce Bachman, Conforming shielded form for electronic component assemblies.
  5. Garg Rajeev ; Prud'Homme Robert K. ; Aksay Ilhan A. ; Janas Victor F. ; TenHuisen Kevor S. ; Huxel Shawn T., Controlled architecture ceramic composites by stereolithography.
  6. Pratt Steven D. ; Muthuswamy Sivakumar ; Pennisi Robert W., Electrical discharge machining electrode and rapid method for fabricating same.
  7. Su, Guo-Kai; Tang, Fu-Di, Encapsulated semiconductor device with flash-proof structure.
  8. Farnworth, Warren M., Energy beam patterning of protective layers for semiconductor devices.
  9. Roberts Jay W., Film frame substrate fixture.
  10. David M. Keicher ; James L. Bullen ; Pierrette H. Gorman ; James W. Love ; Kevin J. Dullea ; Mark E. Smith, Forming structures from CAD solid models.
  11. Scott Patrick M. (Newark Valley NY) Glovatsky Andrew Z. (Ypsilanti MI) Mele Michael A. (Endicott NY), Hermetically sealed high density multi-chip package.
  12. Hedrick Jeffrey Curtis ; Papathomas Kostas ; Rai Amarjit Singh ; Tisdale Stephen Leo ; Viehbeck Alfred, High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer.
  13. Lisa J. Jimarez ; Miguel A. Jimarez, I/C chip assembly.
  14. Kim,Ho Kyoum; Kim,Young Jun; Yu,In Soon, Image sensor module and method for fabricating the same.
  15. Moden,Walter, Imaging system.
  16. Farnworth, Warren M., Layer thickness control for stereolithography utilizing variable liquid elevation and laser focal length.
  17. Tsai, Chung-Che, Light sensitive semiconductor package and fabrication method thereof.
  18. Tsai, Chung-Che, Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package.
  19. Nulman Jaim (Palo Alto CA) Davenport Robert E. (Sunnyvale CA), Low thermal expansion clamping mechanism.
  20. Yoshimura Yoshitaka (Kitakatsuragi JPX) Oura Yasuhiro (Sakurai JPX), Method and apparatus for applying a protective tape on a wafer and cutting it out to shape.
  21. Tandy, William D.; Street, Bret K., Method and apparatus for marking a bare semiconductor die.
  22. Tandy, William D; Street, Bret K., Method and apparatus for marking a bare semiconductor die.
  23. Pennisi Robert W. (Boca Raton FL) Urbish Glenn W. (Coral Springs FL), Method and apparatus for producing molded parts.
  24. Lee Minju,KRX ; Cho Kilho,KRX, Method and apparatus for singulating semiconductor devices.
  25. Piper John G. ; Keith Chris, Method and apparatus to hold integrated circuit chips onto a chuck and to simultaneously remove multiple integrated cir.
  26. Runyon, Robert Carrol; Hor, Che Kiong, Method and wafer for maintaining ultra clean bonding pads on a wafer.
  27. Haas Kevin ; Witte Robert ; Kim Sang, Method for etching photolithographically produced quartz crystal blanks for singulation.
  28. Farnworth, Warren M.; Wood, Alan G.; Doan, Trung Tri, Method for fabricating encapsulated semiconductor components.
  29. Farnworth, Warren M.; Duesman, Kevin G., Method for forming three dimensional structures from liquid with improved surface finish.
  30. Tochioka Takahiro,JPX, Method for producing a polymer composite material.
  31. Robert G. McKenna ; R. Scott Croff, Method of adhering a wafer to wafer tape.
  32. Park Bae-seung,KRX ; Kim Jin-heung,KRX ; Cho Jung-hyun,KRX, Method of and apparatus for laminating a semiconductor wafer with protective tape.
  33. Smith, John W.; Fjelstad, Joseph, Method of assembling a semiconductor chip package.
  34. Kazuma Sekiya JP, Method of dicing workpiece.
  35. Oka, Takahiro, Method of fabricating semiconductor device.
  36. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL) Dorinski Dale W. (Coral Springs FL), Method of forming a three-dimensional printed circuit assembly.
  37. Leedy Glenn Joseph, Method of making dielectrically isolated integrated circuit.
  38. Reiff David E. (Fort Lauderdale FL) Dorinski Dale W. (Coral Springs FL) Hunt Stephen D. (Davie FL), Method of manufacturing a three-dimensional plastic article.
  39. Senoo Hideo,JPX ; Sugino Takasi,JPX, Method of preventing transfer of adhesive substance to dicing ring frame, pressure-sensitive adhesive sheet for use in.
  40. Wachtler, Kurt P., Method of separating semiconductor dies from a wafer.
  41. Grigg, Ford B.; Ocker, James M.; Leininger, Rick A., Methods for labeling semiconductor device components.
  42. Badehi Pierre (Nataf 66 ; Mobile Post Harei Yehuda 90804 ILX), Methods for producing integrated circuit devices.
  43. Akram,Salman, Methods for protecting intermediate conductive elements of semiconductor device assemblies.
  44. Farnworth, Warren M.; Duesman, Kevin G., Methods of fabricating housing structures and micromachines incorporating such structures.
  45. Thomas P. Glenn, Microcircuit die-sawing protector and method.
  46. Ryan Timothy George,GBX ; Harvey Thomas Grierson,GBX, Multifunctional microstructures and preparation thereof.
  47. Keicher David M. ; Miller W. Doyle, Multiple beams and nozzles to increase deposition rate.
  48. Hatta Muneo (Itami JPX), Package for a light-responsive semiconductor chip.
  49. Tom A. Muntifering ; Steven W. Heppler ; Michael B. Ball, Packaging die preparation.
  50. Scranton Alec B. ; Rangarajan Bharath ; Baikerikar Kiran K., Photopolymerizable compositions for encapsulating microelectronic devices.
  51. Hung,Chia Yu; Huang,Chien Ping; Yang,Ke Chuan, Photosensitive semiconductor package and method for fabricating the same.
  52. Muhlebach Andreas,CHX ; Hafner Andreas,CHX ; Van Der Schaaf Paul Adriaan,CHX, Polymerizable composition, process for producing cross-linked polymers and crosslinkable polymers.
  53. Miller W. Doyle ; Keicher David M. ; Essien Marcelino, Precision spray processes for direct write electronic components.
  54. Akram, Salman, Protective structure for bond wires.
  55. Akram, Salman, Protective structures for bond wires.
  56. Jensen Ronald J. ; Spielberger Richard K. ; Nguyen Toan Dinh ; Jacobsen William F., Radiation enhanced chip encapsulant.
  57. Pennisi Robert W. (Boca Raton FL) Urbish Glenn F. (Coral Springs FL), Rapid product realization process.
  58. Akram, Salman, Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof.
  59. Akram Salman, Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices.
  60. Tsai, Yueh-Ying; Hung, Chin-Yuan; Chen, Chang-Fu, Semiconductor package.
  61. Chien-Ping Huang TW, Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention.
  62. Marc Meuris BE; Marc Heyns BE; Paul Mertens BE, Semiconductor processing method for processing discrete pieces of substrate to form electronic devices.
  63. Meuris Marc,BEX ; Mertens Paul,BEX ; Heyns Marc,BEX, Semiconductor processing system for processing discrete pieces of substrate to form electronic devices.
  64. Cuomo ; Jr. Salvatore Ralph (Wappingers Falls NY), Semiconductor wafer dicing fixture.
  65. Akram Salman, Semiconductor wafer processing method.
  66. Connell, Mike; Jiang, Tongbi, Stacked semiconductor package with circuit side polymer layer.
  67. Lu Chih-Yuan,TWX, Step and repeat exposure method for loosening integrated circuit dice from a radiation sensitive adhesive tape backing.
  68. Cho Chan Seob (Kyungki-Do KRX) Chang Hwan Soo (Kyungki-Do KRX) Gil Myung Gun (Daejun-shi KRX), Stepper light control using movable blades.
  69. Farnworth, Warren M.; Johnson, Mark S., Stereolithographic method and apparatus for packaging electronic components and resulting structures.
  70. Farnworth, Warren M., Stereolithographic method for applying materials to electronic component substrates and resulting structures.
  71. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  72. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  73. Warren M. Farnworth, Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  74. Farnworth, Warren M.; Wood, Alan G., Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed.
  75. Akram, Salman, Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed.
  76. Vernon M. Williams, Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods.
  77. Ford B. Grigg ; James M. Ocker ; Rick A. Leininger, Stereolithographically marked semiconductors devices and methods.
  78. Warren M. Farnworth ; Kevin G. Duesman, Surface smoothing of stereolithographically formed 3-D objects.
  79. Grigg, Ford B., Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same.
  80. Grigg, Ford B., Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same.
  81. Grigg, Ford B., Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same.
  82. Larson Charles E. ; Murphy Timothy E. ; Taylor Bryan L. ; Long Jon M. ; Ellis Mark W. ; Riley Vincent L., Thin microelectronic substrates and methods of manufacture.
  83. Derderian, James M.; Draney, Nathan R., Thinned, strengthened semiconductor substrates and packages including same.
  84. Oleg Siniaguine ; Patrick B. Halahan ; Sergey Savastiouk, Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners.
  85. Pratt Steven D. ; Muthuswamy Sivakumar ; Pennisi Robert W., Tooling die insert and rapid method for fabricating same.
  86. Farnworth, Warren M., Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography.
  87. Farnworth, Warren M., Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography.

이 특허를 인용한 특허 (5)

  1. Okada, Kazuo; Kitagawa, Katsuhiko; Yamada, Hiroshi, Semiconductor device.
  2. Shinogi, Hiroyuki; Kitagawa, Katsuhiko; Okada, Kazuo; Yamada, Hiroshi, Semiconductor device and manufacturing method thereof.
  3. Yamada, Hiroshi; Kitagawa, Katsuhiko; Okada, Kazuo; Morita, Yuichi; Shinogi, Hiroyuki; Ishibe, Shinzo; Seki, Yoshinori; Noma, Takashi, Semiconductor device and method of manufacturing the same.
  4. Huang, Shih-Ming; Lin, Chun-Hung; Chen, Yi-Ting; Lin, Wen-Hsin; Chan, Shih-Wei; Chang, Yung-Hsing, Semiconductor package structure and semiconductor process.
  5. Huang, Shih-Ming; Lin, Chun-Hung; Chen, Yi-Ting; Lin, Wen-Hsin; Chan, Shih-Wei; Chang, Yung-Hsing, Semiconductor package structure and semiconductor process.
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