Multiplex (MUX) circuit having a single selection signal and method of generating a MUX output signal with single selection signal
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/094
H03K-017/00
출원번호
US-0992077
(2004-11-19)
등록번호
US-7282958
(2007-10-16)
우선권정보
KR-10-2004-0005309(2004-01-28)
발명자
/ 주소
Rhee,Young Chul
출원인 / 주소
Samsung Electronics Co., Ltd.
대리인 / 주소
Harness, Dickey & Pierce, PLC
인용정보
피인용 횟수 :
5인용 특허 :
1
초록▼
A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selec
A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selection signal for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the selection signal. Generating an output signal from the high-speed MUX circuit may include generating the single selection signal therein and transmitting one of the first and second input signal as a MUX circuit output signal, based on the single selection signal.
대표청구항▼
What is claimed is: 1. A multiplex (MUX) circuit, comprising: a first buffer unit for receiving an inverted version of a first input signal to generate a first buffer unit output signal; a first switch for transmitting the first buffer unit output signal in response to a selection signal; a first i
What is claimed is: 1. A multiplex (MUX) circuit, comprising: a first buffer unit for receiving an inverted version of a first input signal to generate a first buffer unit output signal; a first switch for transmitting the first buffer unit output signal in response to a selection signal; a first inverter for receiving the first input signal to generate a first inverter output signal; a second switch for transmitting the first inverter output signal in response to the selection signal; a second inverter for receiving a second input signal to generate a second inverter output signal; a third switch for transmitting the second inverter output signal in response to the selection signal; a third inverter receiving the first inverter output signal from the second switch and the second inverter output signal from the third switch to generate a third inverter output signal; a second buffer unit for receiving an inverted version of the second input signal to generate a second buffer unit output signal; and a fourth switch for transmitting the second buffer unit output signal in response to the selection signal, wherein the first buffer unit output signal, third inverter output signal and second buffer unit output signal are combined at an output of the third inverter as a MUX circuit output signal. 2. The circuit of claim 1, wherein the first buffer unit is embodied as an inverter connected between the first inverter and first switch, and the second buffer unit is embodied as an inverter connected between the second inverter and fourth switch. 3. The circuit of claim 1, wherein the first switch is embodied as a PMOS transistor receiving the selection signal at its gate, receiving the first buffer unit output signal at its source, and transmitting the first buffer unit output signal from its drain to the output of the third inverter. 4. The circuit of claim 1, wherein the second switch is embodied as a PMOS transistor receiving the selection signal at its gate, receiving the first inverter output signal at its source, and transmitting the first inverter output signal as an input to the third inverter. 5. The circuit of claim 1, wherein the third switch is embodied as a NMOS transistor receiving the selection signal at its gate, receiving the second inverter output signal at its source, and transmitting the second inverter output signal as an input to the third inverter. 6. The circuit of claim 1, wherein the fourth switch is embodied as a NMOS transistor receiving the selection signal at its gate, receiving the second buffer unit output signal at its source, and transmitting the second buffer unit output signal from its drain to the output of the third inverter. 7. A multiplex (MUX) circuit, comprising: a first inverter for receiving a first input signal to generate a first inverter output signal; a second inverter for receiving a second input signal to generate a second inverter output signal; a third inverter for receiving the first inverter output signal to generate a third inverter output signal; a fourth inverter for receiving the second inverter output signal to generate a fourth inverter output signal; a first PMOS transistor receiving a selection signal at its gate, receiving the third inverter output signal at its source, and transmitting the third inverter output signal from its drain as a first output; a second PMOS transistor receiving the selection signal at its gate, receiving the first inverter output signal at its source, and transmitting the first inverter output signal from its drain as a second output; a first NMOS transistor receiving the selection signal at its gate, receiving the second inverter output signal at is source, and transmitting the second inverter output signal from its drain as a third output; a second NMOS transistor receiving the selection signal at its gate, receiving the fourth inverter output at its source, and transmitting the fourth inverter output signal from its drain as a fourth output; and a fifth inverter receiving the second output from the second PMOS transistor and the third output from the first NMOS transistor to generate a MUX circuit output signal. 8. A multiplex (MUX) circuit, comprising: a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs; and a plurality of switches operatively connected to a single selection signal and one of the first input signal and second input signal via an inverter pair for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the single selection signal, wherein each inverter of each of the inverter pairs is directly connected to at least one switches of the plurality of switches. 9. The circuit of claim 8, wherein no inverted selection signal is generated to transmit the MUX circuit output signal. 10. The circuit of claim 8, wherein the plurality of inverter pairs include a first inverter pair and a second inverter pair, the first inverter pair further including: a first inverter for receiving the first input signal to generate a first inverter output signal; a third inverter for receiving the first inverter output signal to generate a third inverter output signal; the second inverter pair further including: a second inverter for receiving the second input signal to generate a second inverter output signal; and a fourth inverter for receiving the second inverter output signal to generate a fourth inverter output signal. 11. The circuit of claim 10, wherein the plurality of switches include: a first PMOS transistor configured to receive the selection signal at its gate, the third inverter output signal at its source, and configured to transmit the third inverter output signal from its drain as a first output; a second PMOS transistor configured to receive the selection signal at its gate, the first inverter output signal at its source, and configured to transmit the first inverter output signal from its drain as a second output; a first NMOS transistor configured to receive the selection signal at its gate, the second inverter output signal at is source, and configured to transmit the second inverter output signal from its drain as a third output; and a second NMOS transistor configured to receive the selection signal at its gate, the fourth inverter output at its source, and configured to transmit the fourth inverter output signal from its drain as a fourth output. 12. The circuit of claim 11, further comprising: a fifth inverter configured to receive the second output from the second PMOS transistor and the third output from the first NMOS transistor to generate the MUX circuit output signal. 13. The circuit of claim 8, wherein a state of the MIJX circuit output signal is a function of the state of one of the selection signal and one of the first and second input signals. 14. The circuit of claim 8, wherein the state of the selection signal determines which of the plurality of switches are turned on and turned off for transmitting at least one inverter output signal representing either the first input signal or the second input signal as the MUX circuit output signal. 15. A method of generating an output signal from a multiplex (MUX) circuit, comprising: generating a single selection signal in the MUX circuit, and transmitting one of a first signal and a second signal, received as inputs to the MUX circuit, through one of a plurality of switches connected to one of the first signal and the second signal and to the single selection signal as a MUX circuit output signal, based on the single selection signal, wherein the single selection signal is directly connected to each of the plurality of switches, and wherein the first single is connected to at least a first two switches of the plurality of switches and the second signal is connected to at least a second two switches of the plurality of switches, the second two switches being different from the first two switches. 16. The method of claim 15, wherein no inverted selection signal is generated in the MUX circuit to transmit the MUX circuit output signal. 17. The method of claim 15, wherein a state of the MUX circuit output signal is a function of the state of one of the selection signal and one of the first and second input signals. 18. The method of claim 15, wherein a state of the selection signal determines whether the first or second input signal is to be transmitted as the MUX circuit output signal.
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이 특허에 인용된 특허 (1)
Rogers Alan C. (Palo Alto CA) Sollars Donald L. (Milpitas CA), High-speed complementary multiplexer.
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