초록 ▼

A network gateway processor architecture including a scalable array of compute processors that function to convert inbound data packets to outbound data packets, an ingress processor coupleable to a first network to receive the inbound data packets and coupled to provide the inbound data packets to

A network gateway processor architecture including a scalable array of compute processors that function to convert inbound data packets to outbound data packets, an ingress processor coupleable to a first network to receive the inbound data packets and coupled to provide the inbound data packets to the compute processors, and an egress processor coupleable to a second network and coupled to the compute processors to collect and forward the outbound data packets to the second network. The ingress processor distributes inbound data packets to the compute processors based on a least load value selected from current load values determined for the respective compute processors of the scalable array. The current load values represent estimated processing completion times for the respective compute processors of the scalable array of compute processors. Preferably, the current load values are dynamically derived with respect to the size of the inbound data packets and the performance of the respective compute processors.

대표청구항 ▼

The invention claimed is: 1. A scalable network gateway processor architecture comprising: a) a scalable array of compute processors implementing a protocol processing function to convert inbound data packets to outbound data packets; b) an ingress processor coupleable to a first network to receive

The invention claimed is: 1. A scalable network gateway processor architecture comprising: a) a scalable array of compute processors implementing a protocol processing function to convert inbound data packets to outbound data packets; b) an ingress processor coupleable to a first network to receive said inbound data packets and coupled to provide said inbound data packets to said scalable array of compute processors, said ingress processor distributing said inbound data packets to said scalable array of compute processors based on a least load value selected from current load values determined for the respective compute processors of said scalable array of compute processors; and c) an egress processor coupleable to a second network and coupled to said scalable array of compute processors to collect outbound data packets from said scalable array of compute processors and send said outbound data packets to said second network, wherein said current load values represent estimated processing completion times for the respective compute processors of said scalable array of compute processors, wherein said current load values are of said inbound data packets to outbound data packets from said ingress processor to said egress processor through said scalable array of compute processors, wherein said ingress processor updates a predetermined one of said current load values on distribution of a predetermined data packet based on the size of said predetermined data packet and the performance data accumulated with respect to a distribution corresponding one of said scalable array of compute processors, and wherein the update of said predetermined one of said current load values is based on an interpolation of the performance data accumulated with respect to a distribution corresponding one of said scalable array of compute processors. 2. A method of dynamically load balancing the distribution of network data packets to plural computer processors within a scalable network gateway processor, said method comprising the steps of: a) developing performance data representing the time to process data packets by an array of packet processors, said performance data being developed with respect to the packet processors of said array of packet processors based on multiple data packet sizes and the unique round trip routes of data packets from ingress to egress with respect to said scalable network gateway processor through said array of packet processors; b) accumulating, with respect to the packet processors of said array of packet processors, load values representing the completion times of data packets pending processing by said array of packet processors, said completion times being estimated based on said performance data; c) distributing data packets to said array of packet processors determined by respective selection of a minimum one of said load values; and d) updating the completion times of data packets pending processing by said array of packet processors upon distribution of data packets to said array of packet processors, wherein the completion times are changed based on said performance data and the size of the data packets distributed, and wherein the respective load values are updated based on an interpolation of the performance data accumulated with respect to said array of packet processors. 3. A scalable processor system supporting dynamic internal load balanced processing of network data packets transferred through said system, said scalable processor system comprising: a) a plurality of compute processors wherein each compute processor implements a data packet processing function to convert first data packets to second data packets; b) an ingress processor coupleable to a first network to receive inbound data packets and coupled to said plurality of compute processors to selectively distribute first data packets to said plurality of compute processors such that each said first data packet is distributed to a respective compute processor determined by said ingress processor to have a current minimum processing load relative to said plurality of compute processors, said current minimum processing load reflecting the respective processing performance of said plurality of compute processors and the size of first data packets respectively pending processing by said plurality of compute processors; and c) an egress processor coupled to said plurality of compute processors to receive said second data packets from said plurality of compute processors, said egress processor being coupleable to a second network to provide outbound data packets to said second network, said scalable processor system maintaining current load values of each said computer processor based on estimated processing completion times for the respective compute processors of said scalable array of compute processors, wherein said current load values are dynamically derived based on performance data accumulated representing each unique round trip route of said inbound data packets to outbound data packets from said ingress processor to said egress processor through said scalable array of compute processors, and wherein the dynamic derivation of said current load values are based on an interpolation of the performance data accumulated with respect to a distribution corresponding one of said plurality of compute processors. 4. The scalable processor system of claim 3 wherein said ingress processor includes performance data reflecting the respective processing performance of said plurality of compute processors for data packets in a predetermined series of sizes. 5. The scalable processor system of claim 4 wherein said ingress processor stores estimated completion times respectively for said plurality of compute processors, wherein said estimated completion times are based on said performance data and the aggregate size of said first data packets distributed respectively to said plurality of compute processors. 6. The scalable processor system of claim 5 wherein said ingress processor determines said current minimum processing load as the minimum delta between a current time and said estimated completion times. 7. The scalable processor system of claim 6 wherein said ingress processor dynamically develops said performance data. 8. The scalable processor system of claim 7 wherein said ingress processor immediately determines to distribute a predetermined first data packet to a predetermined compute processor of said plurality of compute processors where the delta between said current time and said estimated completion time for said predetermined compute processor is less than or equal to zero. 9. The scalable processor system of claim 5 wherein said ingress processor is responsive to busy messages received from said plurality of compute processors and wherein said estimated completion times are further based on said busy messages as received respectively from said plurality of compute processors. 10. The scalable processor system of claim 9 wherein said ingress processor determines said current minimum processing load as the minimum delta between a current time and said estimated completion times. 11. The scalable processor system of claim 10 wherein said ingress processor dynamically develops said performance data.