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Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/485
  • H01L-023/48
출원번호 US-0434524 (2003-05-08)
등록번호 US-7288845 (2007-10-30)
발명자 / 주소
  • Sutardja,Sehat
  • Wu,Albert
  • Lee,Jin Yuan
  • Lin,Mou Shiung
출원인 / 주소
  • Marvell Semiconductor, Inc.
  • MEGIC Corporation
대리인 / 주소
    Wolff & Samson PC
인용정보 피인용 횟수 : 9  인용 특허 : 29

초록

A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the ac

대표청구항

What is claimed is: 1. A structure for enabling wire bond connections over active regions of an integrated circuit (IC) die, comprising: a substrate, in or on which are formed active devices, the die further comprising at least one interconnect metal layer having at least one top level metal contac

이 특허에 인용된 특허 (29)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. McCormick, John P., Bonding pad interface.
  3. Ichikawa Matsuo,JPX, Bonding pad structures for semiconductor integrated circuits.
  4. Bertolet Allan ; Fiore James ; Gramatzki Eberhard, Chip design process for wire bond and flip-chip package.
  5. Buchwalter Leena P. ; Callegari Alessandro Cesare ; Cohen Stephan Alan ; Graham Teresita Ordonez ; Hummel John P. ; Jahnes Christopher V. ; Purushothaman Sampath ; Saenger Katherine Lynn ; Shaw Jane , Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same.
  6. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  8. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
  9. Barth, Hans-Joachim; Felsner, Petra; Kaltalioglu, Erdem; Friese, Gerald, FBEOL process for Cu metallizations free from Al-wirebond pads.
  10. Wollesen Donald L. (Saratoga CA), High conductivity interconnection line.
  11. Kloen Hendrik K.,NLX ; Huiskamp Lodewijk P.,NLX, Integrated circuit device.
  12. Cave Nigel G. ; Yu Kathleen C. ; Farkas Janos, Integrated circuit having a support structure.
  13. Sharma Ravinder K. (Mesa AZ) Geyer Harry J. (Phoenix AZ) Mitchell Douglas G. (Tempe AZ), Metallization scheme providing adhesion and barrier properties.
  14. Wakabayashi Takeshi (Hidaka JPX) Suzuki Akira (Musashino JPX) Yokoyama Shigeru (Chofu JPX), Method for forming a bump electrode for a semiconductor device.
  15. Lin Mou-Shiung,TWX, Method for forming high performance system-on-chip using post passivation process.
  16. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
  17. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  18. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
  19. Lin, Mou-Shiung; Ting, Tah-Kang Joseph, Methods of IC rerouting option for multiple package system applications.
  20. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  21. Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
  22. Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Watanabe Eiji,JPX ; Imamura Kazuyuki,JPX ; Yurino Takahiro,JPX, Semiconductor device with pad structure.
  23. Morozumi, Yukio, Semiconductor devices and methods for manufacturing the same.
  24. Noboru Taguchi JP, Structure for mounting semiconductor device, method of mounting same, semiconductor device, and method of fabricating same.
  25. Saran Mukul, System and method for bonding over active integrated circuits.
  26. Saran Mukul ; Martin Charles A., System and method for reinforcing a bond pad.
  27. Mou-Shiung Lin TW, Top layers of metal for high performance IC's.
  28. Williams Richard K. ; Kasem Mohammad, Vertical power MOSFET having thick metal layer to reduce distributed resistance.
  29. Test, Howard R.; Amador, Gonzalo; Subido, Willmar E., Wire bonding process for copper-metallized integrated circuits.

이 특허를 인용한 특허 (9)

  1. Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
  2. Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
  3. Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
  4. Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
  5. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  6. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  7. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  8. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  9. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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