Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/485
H01L-023/48
출원번호
US-0434524
(2003-05-08)
등록번호
US-7288845
(2007-10-30)
발명자
/ 주소
Sutardja,Sehat
Wu,Albert
Lee,Jin Yuan
Lin,Mou Shiung
출원인 / 주소
Marvell Semiconductor, Inc.
MEGIC Corporation
대리인 / 주소
Wolff & Samson PC
인용정보
피인용 횟수 :
9인용 특허 :
29
초록▼
A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the ac
A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.
대표청구항▼
What is claimed is: 1. A structure for enabling wire bond connections over active regions of an integrated circuit (IC) die, comprising: a substrate, in or on which are formed active devices, the die further comprising at least one interconnect metal layer having at least one top level metal contac
What is claimed is: 1. A structure for enabling wire bond connections over active regions of an integrated circuit (IC) die, comprising: a substrate, in or on which are formed active devices, the die further comprising at least one interconnect metal layer having at least one top level metal contact, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one opening through which is exposed the at least one top level metal contact point; an adhesion layer formed on the passivation layer; and a gold bond pad formed directly on the adhesion layer over the passivation layer, connected to said top level metal contact through said opening, said gold bond pad being formed directly over at least one active device. 2. The structure of claim 1 wherein the gold bond pad is formed over said opening in said passivation layer. 3. The structure of claim 1 wherein a bonding location for the gold bond pad is over said opening in said passivation layer. 4. The structure of claim 1 wherein said opening has a minimum width of about 0.5 μm. 5. The structure of claim 1 wherein said passivation layer comprises one or more layers of inorganic material. 6. The structure of claim 1 wherein said adhesion layer is Ti, Cr, TiW or TiN. 7. The structure of claim 1 wherein said gold bond pad comprises soft Au having a hardness range of less than about 150 Hv, an Au purity larger than about 97%, and a thickness larger than about 1 μm. 8. The structure of claim 1 wherein the adhesion layer is formed over said passivation layer. 9. The structure of claim 1 wherein said passivation opening has a width between 40 μm and 100 μm. 10. A wire connection structure for an integrated circuit (IC) die, comprising: semiconductor means for providing at least one of an active device and a passive device and that includes: dielectric means that is arranged adjacent to said at least one of said active and passive device for providing insulation, metal interconnect means that is arranged adjacent to said at least one of said active and passive device for providing interconnections, wherein said metal interconnect means defines a contact pad, and passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad; and gold bond pad means arranged directly over said passivation means and said active device for absorbing bond pad fabrication stress and for providing a connection to said contact pad through said passivation opening, the gold bond pad means being formed directly on an adhesion layer that is formed on said passivation means and said exposed contact pad. 11. The wire connection structure of claim 10 further comprising wire means for providing a connection to said gold bond pad means and that is bonded to said gold bond pad means in a wire bonding region. 12. The wire connection structure of claim 10 wherein said wire bonding region is formed over said passivation opening. 13. The wire connection structure of claim 10 wherein said passivation means includes one or more layers of inorganic material. 14. The wire connection structure of claim 10 wherein said gold bond pad means includes: a first layer formed over said adhesion layer; a second layer formed over said first layer. 15. The wire connection structure of claim 14 wherein said adhesion layer includes at least one of titanium (Ti), chromium (Cr), titanium tungsten (TiW) and titanium nitride (TiN). 16. The wire connection structure of claim 14 wherein said first layer includes gold that is deposited by sputtering. 17. The wire connection structure of claim 14 wherein said second layer includes gold that is deposited by electroplating. 18. The wire connection structure of claim 14 wherein said second layer has a hardness range of less than about 150 Hv, and wherein said gold of said second layer has a purity that is greater than or equal to about 97% and a thickness that is greater than or equal to 1 μm. 19. A wire connection structure for an integrated circuit (IC) die, comprising: semiconductor means for providing at least one of an active device and a passive device and that includes: dielectric means that is arranged adjacent to said at least one of said active and passive device for providing insulation, metal interconnect means that is arranged adjacent to said at least one of said active and passive device for providing interconnections, wherein said metal interconnect means defines a contact pad, and passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad; gold bond pad means arranged directly over said passivation means and said at least one of said active and passive devices for absorbing wire bonding stress and for providing a connection to said contact means through said passivation opening; and an adhesion layer formed on said passivation means that includes at least one of Ti, Cr, TiW and TiN, the gold bond pad means being formed directly on the adhesion layer; a seed layer formed over said adhesion layer that includes gold; and a bulk layer formed over said seed layer that includes gold. 20. The wire connection structure of claim 19 further comprising a wire that is bonded to said gold bond pad means in a wire bonding region. 21. The wire connection structure of claim 20 wherein said wire bonding region is over said passivation opening. 22. The wire connection structure of claim 19 wherein said bulk layer has a hardness range that is less than or equal to 150 Hv. 23. The wire connection structure of claim 19 wherein said gold has a purity that is greater than or equal to about 97%. 24. The wire connection structure of claim 19 wherein said bulk layer has a thickness that is greater than or equal to about 1 μm. 25. The wire connection structure of claim 19 wherein said seed layer is deposited by sputtering. 26. The wire connection structure of claim 19 wherein said bulk layer is deposited by electroplating. 27. A wire connection structure for an integrated circuit (IC) die, comprising: semiconductor means for providing an active device and that includes: dielectric means that is arranged adjacent to said active device for providing insulation, metal interconnect means that is arranged adjacent to said active device for providing interconnections, wherein said metal interconnect means defines a contact pad, and passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad; an adhesion layer formed on said passivation means and said exposed contact pad; and gold bond pad means arranged directly over said passivation means and said active device for absorbing bond pad fabrication stress and for providing a connection to said contact pad through said passivation opening, the gold bond pad means being formed directly on the adhesion layer. 28. A wire connection structure for an integrated circuit (IC) die, comprising: semiconductor means for providing an active device and that includes: dielectric means that is arranged adjacent to said active device for providing insulation, metal interconnect means that is arranged adjacent to said active device for providing interconnections, wherein said metal interconnect means defines a contact pad, passivation means for insulating said outermost metal interconnect means and including at least one passivation opening that exposes said contact pad; gold bond pad means arranged directly over said passivation means and said active device for absorbing bond pad fabrication stress and for providing a connection to said contact means through said passivation opening; and an adhesion layer formed on said passivation means that includes at least one of Ti, Cr, TiW and TiN, the gold bond pad being formed directly on the adhesion layer, wherein the gold bond pad means includes: a seed layer formed over said adhesion layer that includes gold; and a bulk layer formed over said seed layer that includes gold.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (29)
Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
Buchwalter Leena P. ; Callegari Alessandro Cesare ; Cohen Stephan Alan ; Graham Teresita Ordonez ; Hummel John P. ; Jahnes Christopher V. ; Purushothaman Sampath ; Saenger Katherine Lynn ; Shaw Jane , Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same.
Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
Sharma Ravinder K. (Mesa AZ) Geyer Harry J. (Phoenix AZ) Mitchell Douglas G. (Tempe AZ), Metallization scheme providing adhesion and barrier properties.
Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.