초록 ▼

A semiconductor material (5) is grown in the windows (4) of a patterned mask layer (3) on a substrate (1). The semiconductor material (5) grows together over the mask layer (3) with semiconductor material (5) from adjacent windows to form a largely planar surface (7), which is suitable for the furt

A semiconductor material (5) is grown in the windows (4) of a patterned mask layer (3) on a substrate (1). The semiconductor material (5) grows together over the mask layer (3) with semiconductor material (5) from adjacent windows to form a largely planar surface (7), which is suitable for the further growth of a component layer sequence (9). Through the choice of a substrate (1) having a smaller thermal expansion coefficient than the semiconductor material (5), particularly strong tensile stresses occur in the semiconductor material (5) or the component layer sequence (9) during cooling, which stresses lead to cracking. Since the semiconductor material (5) that has grown together forms a so-called coalescence region (6), having a high density of imperfections in the crystal lattice, these thermally governed cracks (13) are more likely to occur in this region. If the semiconductor bodies are singulated along these regions, these regions high in defects can be removed during the singulation, and a semiconductor body of high crystal quality can be mass produced.

대표청구항 ▼

What is claimed is: 1. A method for fabricating a plurality of semiconductor bodies, comprising the steps of: (a) forming a mask layer on a substrate, which mask layer has a plurality of windows to the substrate, thus giving rise to uncovered locations of the substrate; (b) growing a semiconductor

What is claimed is: 1. A method for fabricating a plurality of semiconductor bodies, comprising the steps of: (a) forming a mask layer on a substrate, which mask layer has a plurality of windows to the substrate, thus giving rise to uncovered locations of the substrate; (b) growing a semiconductor material onto the uncovered locations of the substrate in such a way that it grows over the mask layer and then grows together over the mask layer between adjacent windows where it forms a coalescence region; (c) growing a component layer sequence onto the semiconductor material; and (d) singulating the composite comprising substrate, mask layer, semiconductor material and component layer sequence into individual semiconductor chips along each coalescence region. 2. The method as claimed in claim 1, wherein a change in temperature which might lead to cracking in the semiconductor material is avoided between steps (b) and (c). 3. The method as claimed in claim 1, wherein the substrate comprises a material whose thermal expansion coefficient is less than the expansion coefficient of the semiconductor material and/or the component layer sequence. 4. The method as claimed in claim 1, wherein the thickness of the substrate is greater than the total thickness of the semiconductor material and the component layer sequence. 5. The method as claimed in claim 1, wherein, before step step (d) the composite is cooled below the growth temperature. 6. The method as claimed in claim 5, wherein thermally induced cracks occur during cooling in the semiconductor material and/or in the component layer sequence. 7. The method as claimed in claim 1, wherein the semiconductor material has a plurality of layers of different compositions. 8. The method as claimed in claim 1, wherein, before step (a), a buffer layer is applied to the substrate and the windows of the mask layer are formed toward the buffer layer and the semiconductor material is grown in the windows on the buffer layer. 9. The method as claimed in claim 1, wherein, after step (a), a buffer layer is applied to the substrate in the windows of the mask layer and the semiconductor material is subsequently grown in the windows on the buffer layer. 10. The method as claimed in claim 1, wherein the semiconductor material is grown on using an ELOG technique. 11. The method as claimed in claim 1, wherein the semiconductor material and/or the component layer sequence is grown on by means of an MOVPE method. 12. The method as claimed in claim 11, wherein, in step (b), a plurality of three-dimensional structures are grown on in the windows. 13. The method as claimed in claim 11, wherein, in step (b), a plurality of three-dimensional structures are grown on in the windows, which structures have one of the following forms: a pyramid shape or a truncated pyramid shape. 14. The method as claimed in claim 13, wherein the growth is set in such a way that it essentially takes place in a direction which is perpendicular to the facets of the three-dimensional structures. 15. The method as claimed in claim 1, wherein the semiconductor material grown on in step (b) has a largely planar surface. 16. The method as claimed in claim 1, wherein gaps arise between the mask layer and the semiconductor material deposited in step (b). 17. The method as claimed in claim 1, wherein the mask layer has a lattice-like or mesh-like structure. 18. The method as claimed in claim 17, wherein the windows in the lattice-like mask layer define a chip grid. 19. The method as claimed in claim 1, wherein the windows are formed in step (a) in one of the following forms: triangular, quadrangular, circular or hexagonal. 20. The method as claimed in claim 1, wherein the form and size of the windows determine the contour and size of the semiconductor bodies to be fabricated. 21. The method as claimed in claim 1, wherein webs of the mask layer are provided between the windows and the web widths are of the order of magnitude of the width of separating structures for singulation of the composite. 22. The method as claimed in claim 21, wherein the separating structures are sawing trenches. 23. The method as claimed in claim 1, wherein, after step (c), crack initiators are produced on the surface of the component layer sequence remote from the substrate, in defect regions. 24. The method as claimed in claim 23, wherein the crack initiators are produced before a change in temperature takes place which may lead to cracking in the semiconductor material and/or the component layer sequence. 25. The method as claimed in claim 1, wherein the component layer sequence and the semiconductor material are removed after the cooling of the composite in the vicinity of a coalescence region. 26. The method as claimed in claim 1, wherein, after step (d), a residual coalescence region and/or defect region are/is removed by means of etching. 27. The method as claimed in claim 1, wherein the mask layer contains silicon nitride. 28. The method as claimed in claim 1, wherein the semiconductor material and/or the component layer sequence contains a compound of elements from the third and fifth main groups. 29. The method as claimed in claim 1, wherein the semiconductor material and/or the component layer sequence contains a nitride compound semiconductor material. 30. The method as claimed in claim 1, wherein the semiconductor material and/or the component layer sequence contains a material based on InxAlyGA1-x-yN where 0≦x≦1, 0≦y≦1 and x+y≦1. 31. The method as claimed in claim 1, wherein the substrate contains silicon, silicon carbide and/or sapphire. 32. An electronic semiconductor body, wherein the semiconductor body is fabricated according to the method as claimed in claim 1. 33. The electronic semiconductor as claimed in claim 32, wherein the electronic semiconductor is a radiation-emitting semiconductor chip. 34. The electronic semiconductor body as claimed in claim 32, wherein the electronic semiconductor body forms one of the following radiation-emitting semiconductor chips: a light-emitting diode chip or a laser diode chip. 35. A method for fabricating a plurality of semiconductor bodies, comprising the steps of: (a) forming a mask layer on a substrate, which mask layer has a plurality of windows to the substrate, thus giving rise to uncovered locations of the substrate; (b) growing a semiconductor material onto the uncovered locations of the substrate in such a way that it grows over the mask layer and then grows together over the mask layer between adjacent windows where it forms a coalescence region; (c) growing a component layer sequence onto the semiconductor material; (c1) producing, in defect regions, crack initiators on the surface of the component layer sequence remote from the substrate by selective in-situ etching in the epitaxy reactor; and (d) singulating the composite comprising substrate, mask layer, semiconductor material and component layer sequence into individual semiconductor chips along each coalescence region. 36. A method for fabricating a plurality of semiconductor bodies, which comprises the steps of: (a) forming a mask layer on a substrate, which mask layer has a plurality of windows to the substrate and onto which mask layer a semiconductor material that is to be grown on to the substrate in a later method step can grow significantly less well in comparison with the substrate; (b) growing the semiconductor material onto the substrate in such a way that it grows over the mask layer, proceeding from the windows, and then grows together over the mask layer between adjacent windows, where it forms a coalescence region; (c) growing a component layer sequence onto the semiconductor material; and (d) singulating the composite comprising substrate, mask layer, semiconductor material and component layer sequence into individual semiconductor chips along each coalescence region.