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Self-organizing data driven learning hardware with local interconnections 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 US-0174038 (2002-06-18)
등록번호 US-7293002 (2007-11-06)
발명자 / 주소
  • Starzyk,Janusz A.
출원인 / 주소
  • Ohio University
대리인 / 주소
    Calfee, Halter & Griswold LLP
인용정보 피인용 횟수 : 5  인용 특허 : 28

초록

A method for organizing processors to perform artificial neural network tasks is provided. The method provides a computer executable methodology for organizing processors in a self-organizing, data driven, learning hardware with local interconnections. A training data is processed substantially in p

대표청구항

What is claimed is: 1. A self-organizing apparatus, comprising: a plurality of artificial neurons arranged in multiple layers; a plurality of initial interconnections interconnecting the plurality of artificial neurons to form an initial configuration of a self-organizing learning array in which le

이 특허에 인용된 특허 (28)

  1. Glier Michael T. (Chepachet RI) Cole John (Northboro MA) Laird Mark (Milford MA), Adaptive classifier having multiple subnetworks.
  2. Tawel Raoul (S. Pasadena CA), Adaptive neuron model-an architecture for the rapid learning of nonlinear topological transformations.
  3. Baji Toru (Burlingame CA) Noguchi Kouki (Kokubunji CA JPX) Nakagawa Tetsuya (Millbrae CA) Tonomura Motonobu (Kodaira JPX) Akimoto Hajime (Mobara JPX) Masuhara Toshiaki (Tokyo JPX), Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition.
  4. Swenson Richard M. (Ridgecrest CA), Artificial neural system with binary weighting by equal resistor network.
  5. Keeler, James D.; Hartman, Eric J.; Godbole, Devendra B.; Piche, Steve; Arbila, Laura; Ellinger, Joshua; Ferguson, II, R. Bruce; Krauskop, John; Kempf, Jill L.; O'Hara, Steven A.; Strauss, Audrey; Te, Automated method for building a model.
  6. Duong Tuan A. (Pasadena CA) Daud Taher (Tujunga CA) Thakoor Anilkumar P. (Covina CA), Cascaded VLSI neural network architecture for on-line learning.
  7. Robert W. Means ; Richard Calmbach, Cortronic neural networks with distributed processing.
  8. Swenson Richard M. (P.O. Box 470 Ridgecrest CA 93555) Cole ; III John C. (7417 92nd Pl. S.E. Mercer Island WA 98040) Holmes Steve L. (2514 230th Ave. NE. Redmond WA 98053) Ekas Paul B. (11810 28th Av, Digitally weighted neuron for artificial neural network.
  9. Helsper, David; Wilkinson, Clayton; Zack, Robert; Tatum, John T.; Jannarone, Robert J.; Harzog, Bernd, Enhanced computer performance forecasting system.
  10. Mueller Paul H. (King of Prussia PA) Van Der Spiegel Jan (Philadelphia PA), General purpose neural computer.
  11. Carson John C. (Corona del Mar CA), Hardware for electronic neural network.
  12. Alhalabi Bassem A., Hybrid chip-set architecture for artificial neural network system.
  13. Asai Mitsuo (Kokubunji JPX) Masuda Noboru (Kokubunji JPX) Yasunaga Moritoshi (Kawaguchi JPX) Yagyu Masayoshi (Kokubunji JPX) Yamada Minoru (Hanno JPX) Shibata Katsunari (Kokubunji JPX), Information processing apparatus.
  14. Tang Zheng,JPX, Learning methods in binary systems.
  15. Connell Jonathan Hudson (Cortlandt-Manor NY) Mohan Rakesh (Stamford CT) Bolle Rudolf Maarten (Bedford Hills NY), Learning system with prototype replacement.
  16. Swenson Richard M. (Ridgecrest CA) Andes David K. (Ridgecrest CA) Witcher Donald H. (Ridgecrest CA) Licklider Robert A. (Ridgecrest CA) Barbieri James F. (Ridgecrest CA), Method and circuits for neuron perturbation in artificial neural network memory modification.
  17. Keeler James David ; Hartman Eric Jon ; Ferguson Ralph Bruce, Method for operating a neural network with missing and/or incomplete data.
  18. Tannhof,Pascal; de Tremiolles,Ghislain Imbert, Method to improve the data transfer rate between a computer and a neural network.
  19. Carrieri Arthur H. (Abingdon MD) Lim Pascal I. (Baltimore MD), Neural network computing system for pattern recognition of thermoluminescence signature spectra and chemical defense.
  20. Padden Robin (Roy UT), Neural network disk drive read channel pattern detector.
  21. Watanabe Takao (Inagi JPX) Kimura Katsutaka (Akishima JPX) Itoh Kiyoo (Higashikurume JPX) Kawajiri Yoshiki (Hachioji JPX), Neural network processing system using semiconductor memories.
  22. Kuwata Ryuichi (Tokyo JPX), Neural network system having minimum energy function value.
  23. Keeler James D. (Austin TX) Hartman Eric J. (Austin TX), Neural network with semi-localized non-linear mapping of the input space.
  24. Lo James Ting-Ho (Ellicott City MD) Yu Lei (Adelphi MD), Optimal filtering by neural networks with range extenders and/or reducers.
  25. Lo James T. (10210 Sunway Ter. Ellicott City MD 21042), Optimal filtering by recurrent neural networks.
  26. Hori Toshikazu ; Paillet Guy ; Woo Jeffrey M., Parallel associative learning memory for a standalone hardwired recognition system.
  27. Wood Laurence F. (Medway MA), Training neural networks.
  28. Brooks William O. (Aloha OR) Cossitt Alan J. (Portland OR) Helm Richard K. (Aloha OR) Johnson Louis J. (Beaverton OR) McNamee Raymond E. (Boring OR), Training system for neural networks and the like.

이 특허를 인용한 특허 (5)

  1. Leedy, Glenn J, Configurable vertical integration.
  2. Leedy, Glenn J, Configurable vertical integration.
  3. Leedy, Glenn J., Configurable vertical integration.
  4. Kranner,Gerhard, Method for the computer-supported generation of prognoses for operative systems and a system for the generation of prognoses for operative systems.
  5. Sasagawa, Yukihiro, Neural network system.
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