초록 ▼

A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit havi

A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

대표청구항 ▼

What is claimed is: 1. An apparatus comprising: a multi-frequency phase-locked loop (PLL) circuit including a feedback divider circuit; a storage to store a plurality of values; at least one input terminal coupled to select a particular one of the stored values; and wherein the multi-frequency PLL

What is claimed is: 1. An apparatus comprising: a multi-frequency phase-locked loop (PLL) circuit including a feedback divider circuit; a storage to store a plurality of values; at least one input terminal coupled to select a particular one of the stored values; and wherein the multi-frequency PLL circuit is coupled to output one of a plurality of selectable output signals having an arbitrary frequency relationship to each other, each of the selectable output signals corresponding to one of the stored values, the one of the plurality of the selectable output signals that is output by the PLL circuit corresponding to the particular one of the stored values, the particular one of the stored values being coupled to determine, at least in part, a divide ratio of the feedback divider circuit; and wherein the phase-locked loop circuit is fractional-N loop circuit. 2. The apparatus as recited in claim 1 wherein the at least one input terminal forms at least a part of a digital communications interface coupled to receive control informational to select the particular one of the stored values. 3. The apparatus as recited in claim 1 wherein the at least one input terminal is one of one or more frequency select input terminals coupled to select the particular one of the stored values according to the logical value of the one or more frequency select input terminals. 4. The apparatus as recited in claim 3 wherein the apparatus has two frequency select input terminals coupled to select one of four stored values to control the feedback divider ratio. 5. The apparatus as recited in claim 1 wherein respective frequencies of the plurality of selectable output signals include at least four frequencies of a group of frequencies consisting of approximately 155.52 MHz 166.63 MHz, 167.33 MHz, 161.13 MHz, 172.64 MHz, 173.37 MHz, 164.35 MHz, and 176.83 MHz. 6. The apparatus as recited in claim 1 wherein the PLL circuit further comprises a phase detector circuit coupled to receive a timing reference signal and an output of the feedback divider circuit, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and the apparatus further comprises one or more divider circuits coupled to an output of the oscillator circuit, wherein the at least one input terminal further selects one or more respective divide ratios of the one or more divider circuits. 7. The apparatus as recited in claim 1 wherein the apparatus further comprises a single resonating element disposed in a package with an integrated circuit, the integrated circuit including the PLL circuit, the storage and the at least one input terminal. 8. The apparatus as recited in claim 7 wherein the single resonating element is a low frequency crystal oscillator. 9. The apparatus as recited in claim 1 further comprising a voltage control input to adjust a frequency of the phase-locked loop circuit output signal and wherein the voltage control input is coupled to further control the divide ratio of the feedback divider circuit according to a voltage present on the voltage control input. 10. The apparatus as recited in claim 9 wherein the plurality of selectable output frequencies include at least four of a group of frequencies including frequencies of approximately 622.08 MHz, 666.51 MHz, 669.33 MHz, 644.53 MHz, 690.57 MHz, 693.48 MHz, 657.42 MHz, and 707.35 MHz. 11. The apparatus as recited in claim 9 wherein the apparatus is a line card in a communications network and the apparatus further comprises a phase detector and loop filter coupled to control the voltage control input. 12. The apparatus as recited in claim 1 further comprising one of a crystal oscillator and a surface acoustic wave (SAW) resonator to supply the timing reference signal. 13. The apparatus as recited in claim 1 wherein the storage to store the plurality of stored values utilized to control, at least in part, the feedback divider value is a nonvolatile storage. 14. A method comprising: selecting a frequency of an output signal from a phase-locked loop (PLL) circuit to be one of a plurality of selectable output frequencies having an arbitrary relationship to each other, the selection being determined according to a frequency select value determined by a frequency selection mechanism that utilizes at least one input terminal of a device incorporating the PLL circuit; controlling a divide ratio of a feedback divider circuit in the phase-locked loop circuit according to the frequency select value; selecting one of a plurality of stored values according to the frequency select value; utilizing the stored value to determine, at least in part, the divide ratio; and determining the divide ratio further according to a value of an analog voltage on a voltage control input terminal, thereby selecting the frequency. 15. The method as recited in claim 14 further comprising utilizing a digital communication interface to select the frequency select value by writing to a register in the device. 16. The method as recited in claim 14 further comprising determining the frequency select value according to a static logical value on one or more input terminals. 17. The method as recited in claim 14 wherein the plurality of selectable output frequencies include at least four of a group of frequencies including the frequencies of approximately 622.08 MHz, 666.51 MHz, 669.33 MHz, 644.53 MHz, 690.57 MHz, 693.48 MHz, 657.42 MHz, and 707.35 MHz. 18. The method as recited in claim 14 wherein the plurality of selectable output frequencies include at least four frequencies of a group of frequencies including the frequencies of approximately 155.52 MHz, 166.63 MHz, 167.33 MHz, 161.13 MHz, 172.64 MHz, 173.37 MHz, 164.35 MHz, and 176.83 MHz. 19. The method as recited in claim 14 further comprising: storing control values corresponding to respective output frequencies in a non-volatile memory; and selecting at least one of the stored control values according to the frequency select value. 20. The method as recited in claim 14 further comprising further controlling the divide ratio according to a temperature compensation circuit. 21. The method as recited in claim 14 further comprising controlling a divide ratio of one or more additional divider circuits coupled to an output of a controllable oscillator circuit in the PLL circuit, according to the frequency select value. 22. The method as recited in claim 16 further comprising using two input terminals to select between four possible frequencies. 23. An integrated circuit comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator; and means for selecting for output from the PLL circuit an output signal having one of a plurality frequencies having an arbitrary frequency relationship to each other, according to a value of one or more input terminals of the integrated circuit; and wherein the phase-locked loop circuit is a fractional-N loop circuit. 24. The apparatus as recited in claim 23 where the means for selecting includes means for controlling a divide ratio of the feedback divider circuit. 25. A line card for use in a communications system comprising: an integrated circuit including, a first phase-locked loop (PLL) circuit having a feedback divider circuit; a storage to store a plurality of values; one or more input terminals coupled to select a particular one of the stored values; wherein the PLL circuit is coupled to output one of a plurality of selectable output signals having an arbitrary frequency relationship to each other, each of the selectable output signals corresponding to one of the stored values, the one of the plurality of the selectable output signals that is output by the first PLL circuit corresponding to a particular one of the stored values, the particular one of the stored values being coupled to determine, at least in part, a divide ratio of the feedback divider circuit; a voltage control input to adjust a frequency of the phase-locked loop circuit output signal and wherein the voltage control input is coupled to further control the divide ratio of the feedback divider circuit according to a voltage present on the voltage control input; a single resonator coupled directly to the integrated circuit; and a clock scaling phase locked loop including a phase detector and loop filter coupled to an output of the first phase-locked loop and a timing reference signal and coupled to provide a voltage signal coupled to the voltage control input.