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Printed wiring boards possessing regions with different coefficients of thermal expansion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/03
  • H05K-001/00
  • H05K-001/18
  • H05K-007/00
출원번호 US-0214690 (2005-08-29)
등록번호 US-7301105 (2007-11-27)
발명자 / 주소
  • Vasoya,Kalu K.
출원인 / 주소
  • Stablcor, Inc.
대리인 / 주소
    Kauth, Pomeroy, Peck & Bailey LLP
인용정보 피인용 횟수 : 49  인용 특허 : 34

초록

Printed wiring boards are disclosed that include regions having different coefficients of thermal expansion. In one aspect of the invention, the regions can be matched to the coefficients of thermal expansion of devices mounted on the printed wiring board. In one embodiment, the invention includes a

대표청구항

What is claimed is: 1. A printed wiring board comprising: a layer including a base material and at least one planar insert material that are combined using a resin; wherein the base material and planar insert material are located within the same plane; wherein the base material comprises the majori

이 특허에 인용된 특허 (34)

  1. Collins Larry C. (Morton IL) Cook James G. (Hanna City IL) Hoffman John P. (Peoria IL), Apparatus for improving the power dissipation of a semiconductor device.
  2. Durand David (Providence RI) Vieau David P. (East Greenwich RI) Chu Ang-Ling (Cranston RI) Wei Tai S. (Warwick RI), Assembly using electrically conductive cement.
  3. Enomoto Eyo (Oogaki JPX), Ceramic wiring board and its production.
  4. McClanahan Robert F. (Valencia CA) Washburn Robert D. (Malibu CA), Dielectric vias within multi-layer 3-dimensional structures/substrates.
  5. Kei Nakamura JP; Masakazu Sugimoto JP; Yasushi Inoue JP; Megumu Nagasawa JP; Takuji Okeyui JP; Masayuki Kaneto JP; Shinya Ota JP, Double-sided circuit board and multilayer wiring board comprising the same and process for producing double-sided circuit board.
  6. Donald S. Farquhar ; Robert M. Japp ; John M. Lauffer ; Konstantinos I. Papathomas, Formation of multisegmented plated through holes.
  7. Bupp, James R.; Farquhar, Donald S.; Jimarez, Lisa J., High performance packaging platform and method of making same.
  8. Leibowitz Joseph D. (Culver City CA), High-frequency multilayer printed circuit board.
  9. Brandt Lutz W. ; Matijasevic Goran ; Gandhi Pradeep R., Individual embedded capacitors for laminated printed circuit boards.
  10. Japp, Robert M.; Markovich, Voya R.; Papathomas, Konstantinos I., Laminate circuit structure and method of fabricating.
  11. Japp Robert M. ; Poliks Mark D., Low CTE power and ground planes.
  12. Zweben Carl H. (Devon PA) Mogle Rodman A. (Clinton NY) Rodini ; Jr. Benjamin T. (Wayne PA) Thaw Charles L. (Phoenixville PA), Low-thermal-expansion, heat conducting laminates having layers of metal and reinforced polymer matrix composite.
  13. Haze, Takayuki; Yabuuchi, Tsuneo, Method for producing a double-sided wiring board.
  14. Leibowitz Joseph D. (Culver City CA), Method of fabricating multilayer printed circuit board structure.
  15. Schmidt Walter (Zrich CHX) Martinelli Marco (Neftenbach CHX), Method of making a laminated structure with shear force delamination resistance.
  16. Middelman Erik,NLX ; Zuuring Pieter Hendrik,NLX, Method of manufacturing a multilayer printed wire board.
  17. Ogihara Satoru (Hitachi JPX) Ura Mitsuru (Hitachi JPX) Suzuki Yoshihiro (Hitachi JPX), Multilayer circuit board.
  18. Sasaki, Masayuki, Multilayer circuit board having a capacitor and process for manufacturing same.
  19. Bovensiepen Kurt,DEX ; Ulmer Helmut,DEX ; Messarosch Gerhard,DEX, Multilayer circuit board having at least one core substrate arranged therein.
  20. Leibowitz Joseph D. (Culver City CA), Multilayer printed circuit board structure.
  21. Tani,Motoaki; Hayashi,Nobuyuki; Abe,Tomoyuki; Takahashi,Yasuhito; Shuto,Takashi, Multilayer wiring board.
  22. Hawker, Craig Jon; Hedrick, James L.; Miller, Robert D.; Volksen, Willi, Porous dielectric material and electronic devices fabricated therewith.
  23. Hatakeyama Akihito,JPX ; Nakatani Seiichi,JPX ; Kawakita Kouji,JPX ; Sogou Hiroshi,JPX ; Ogawa Tatsuo,JPX ; Kojima Tamao,JPX, Printed circuit board and method of manufacturing the same.
  24. Ozaki Yosuke,JPX, Printed circuit board and printed circuit board base material.
  25. Alan D. Conder, Printed circuit board for a CCD camera head.
  26. Kramer Jesse J. ; Madura Jeffrey R. ; Smith Carl Richard, Printed wiring board structure having continuous graphite fibers.
  27. Jensen Warren M. (Kirkland WA), Printed wiring board substrates for ceramic chip carriers.
  28. Walter Schmidt CH; Marco Martinelli CH, Process for producing connecting conductors.
  29. Schmidt Walter,CHX ; Schmid Hermann,CHX, Process for structuring polymer films.
  30. Schmidt Walter (Zrich CHX) Martinelli Marco (Neftenbach CHX), Process for the production of printed circuit boards with extremely dense wiring using a metal-clad laminate.
  31. Desai Jay (Corona CA), Rigid flex printed circuit configuration.
  32. Nagamatsu Hiroshi (Hiratsuka JPX) Iwasaki Kaname (Hiratsuka JPX), Substrate for a printed circuit board.
  33. Afzali-Ardakani Ali (Yorktown Heights NY) Gotro Jeffrey T. (Endwell NY) Hedrick Jeffrey C. (Peekskill NY) Papathomas Konstantinos (Endicott NY) Patel Niranjan M. (Wappingers Falls NY) Shaw Jane M. (R, Toughened polycyanurate resins containing particulates.
  34. Tani, Motoaki; Hayashi, Nobuyuki; Abe, Tomoyuki; Takahashi, Yasuhito; Saeki, Yoshiyasu, Wiring board with core layer containing inorganic filler.

이 특허를 인용한 특허 (49)

  1. Rathburn, James, Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection.
  2. Rathburn, James, Bumped semiconductor wafer or die level electrical interconnect.
  3. Rathburn, James, Compliant conductive nano-particle electrical interconnect.
  4. Rathburn, James, Compliant conductive nano-particle electrical interconnect.
  5. Rathburn, James, Compliant core peripheral lead semiconductor socket.
  6. Rathburn, James, Compliant core peripheral lead semiconductor test socket.
  7. Rathburn, James, Compliant printed circuit area array semiconductor device package.
  8. Rathburn, James, Compliant printed circuit semiconductor package.
  9. Rathburn, James, Compliant printed circuit semiconductor package.
  10. Rathburn, James, Compliant printed circuit semiconductor tester interface.
  11. Rathburn, James, Compliant printed circuit socket diagnostic tool.
  12. Rathburn, James, Compliant printed circuit wafer level semiconductor package.
  13. Rathburn, James, Compliant printed circuit wafer probe diagnostic tool.
  14. Rathburn, James, Compliant printed flexible circuit.
  15. Rathburn, James, Compliant wafer level probe assembly.
  16. Rathburn, James, Composite polymer-metal electrical contacts.
  17. Rathburn, James, Copper pillar full metal via electrical circuit structure.
  18. Rathburn, Jim, Copper pillar full metal via electrical circuit structure.
  19. Rathburn, James, Direct metalization of electrical circuit structures.
  20. Rathburn, James, Electrical connector insulator housing.
  21. Rathburn, James, Electrical interconnect IC device socket.
  22. Rathburn, James, Electrical interconnect IC device socket.
  23. Rathburn, James, Fusion bonded liquid crystal polymer circuit structure.
  24. Schneider, Douglas; Davis, William E., Graphene-based thermal management cores and systems and methods for constructing printed wiring boards.
  25. Rathburn, James, High performance electrical circuit structure.
  26. Rathburn, James, High performance surface mount electrical interconnect.
  27. Rathburn, James, High performance surface mount electrical interconnect.
  28. Rathburn, James, High performance surface mount electrical interconnect.
  29. Rathburn, James, High performance surface mount electrical interconnect with external biased normal force loading.
  30. Rathburn, James, High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly.
  31. Rathburn, James, Hybrid printed circuit assembly with low density main core and embedded high density circuit regions.
  32. Rathburn, James J., Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction.
  33. Rathburn, James J., Mechanical contact retention within an electrical connector.
  34. Rathburn, James, Metalized pad to electrical contact interface.
  35. Rathburn, James, Method of forming a semiconductor socket.
  36. Rathburn, James, Method of making a compliant printed circuit peripheral lead semiconductor package.
  37. Rathburn, James, Method of making a compliant printed circuit peripheral lead semiconductor test socket.
  38. Rathburn, James J., Method of making an electrical connector having electrodeposited terminals.
  39. Rathburn, Jim, Method of making an electronic interconnect.
  40. Rathburn, James, Performance enhanced semiconductor socket.
  41. Vasoya, Kalu K., Processes for manufacturing printed wiring boards.
  42. Rathburn, James, Resilient conductive electrical interconnect.
  43. Rathburn, James, Selective metalization of electrical connector or socket housing.
  44. Rathburn, Jim, Selective metalization of electrical connector or socket housing.
  45. Rathburn, James, Semiconductor device package adapter.
  46. Rathburn, James, Semiconductor die terminal.
  47. Rathburn, James, Semiconductor socket with direct selective metalization.
  48. Rathburn, James, Simulated wirebond semiconductor package.
  49. Rathburn, James, Singulated semiconductor device separable electrical interconnect.
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