IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0857134
(2004-05-28)
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등록번호 |
US-7302282
(2007-11-27)
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발명자
/ 주소 |
- McKim, Jr.,James B.
- Hyde,John W.
- Vulovic,Marko
- Chan,Buck H.
- Kenny,John F.
- Carlson,Richard A.
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출원인 / 주소 |
- Agilent Technologies, Inc.
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인용정보 |
피인용 횟수 :
12 인용 특허 :
7 |
초록
▼
An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link
An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.
대표청구항
▼
What is claimed is: 1. An apparatus comprising: a housing having a controller and a back plane, said housing accepting at least first and second modules for interconnection with said back plane, said back plane distributing power to each module, said backplane also providing a dedicated serial comm
What is claimed is: 1. An apparatus comprising: a housing having a controller and a back plane, said housing accepting at least first and second modules for interconnection with said back plane, said back plane distributing power to each module, said backplane also providing a dedicated serial communication link from said controller to respective ones of said modules, each communication link having no more than a data out line, a data in line and a clock line, each clock line being derived from one clock source, wherein all connections between said at least first and second modules interconnect with said back plane through galvanic isolators and wherein said controller transmits send packets over said data out lines and wherein a start of frame signal for each said send packet occurs on a single edge of said clock source. 2. An apparatus as recited in claim 1 wherein said communications link comprises a JTAG communications link. 3. An apparatus as recited in claim 1 wherein said galvanic isolators are disposed on each said at least first and second modules. 4. An apparatus as recited in claim 1 wherein said first module comprises a power supply. 5. An apparatus as recited in claim 4 wherein said first module further comprises first waveform generator and first digitizer for control and measurement of an output voltage and second waveform generator and second digitizer for control and measurement of an output current. 6. An apparatus as recited in claim 1 wherein said first module comprises an electronic load. 7. An apparatus as recited in claim 6 wherein said electronic load further comprises a waveform generator for control of an input current and first and second digitizers for control and measurement of an input voltage. 8. An apparatus as recited in claim 6 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current. 9. An apparatus as recited in claim 6 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current adapted to maintain a constant resistance load. 10. An apparatus as recited in claim 1 wherein said controller transmits a send data packet on each said data out line simultaneously and synchronized to said clock source, and said at least first and second modules each transmits a receive packet on said data in line synchronized to said clock source wherein said receive packet is delayed from said send packet. 11. An apparatus as recited in claim 10 wherein said send packet is delayed from said receive packet by an integer number of clock cycles. 12. An apparatus as recited in claim 10 wherein said send packet is delayed from said receive packet by two cycles of said clock. 13. An apparatus as recited in claim 10 wherein a first send packet and a first receive packet are sent in a single communications frame, and wherein said first receive packet comprises a status bit and said first send packet comprises a responsive bit to said status bit, wherein said status bit is sent prior to said responsive bit, wherein said responsive bit is sent to selected receiving modules, and wherein said receiving modules initiate an action upon receipt of said responsive bit. 14. An apparatus as recited in claim 13 wherein said status bit comprises a fast protect bit indicating a condition in at least said first module that warrants a response by said second module. 15. An apparatus as recited in claim 13 wherein said response comprises an output inhibit. 16. An apparatus as recited in claim 12 wherein a first bit for each said receive packet occurs on a single edge of said clock source. 17. An apparatus as recited in claim 1 wherein said controller transmits a send data packet on each said data out line synchronized to said clock source, said send data packet containing at least one trigger bit. 18. An apparatus as recited in claim 17 wherein said at least one trigger bit is received by said first module and initiates an operation in said first module. 19. An apparatus as recited in claim 1 wherein said controller transmits a send data packet on each said data out line synchronized to said clock source, each said send data packet containing a respective trigger signal at a same bit location in each said send packet. 20. An apparatus as recited in claim 19 wherein said respective trigger signals are received by said at least first and second modules synchronized with a single edge of said clock source and initiate an operation in each said module at a substantially similar time. 21. An apparatus as recited in claim 17 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a separate action in said module. 22. An apparatus as recited in claim 17 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a same action in said module. 23. An apparatus as recited in claim 1 wherein said controller transmits each said send data packet during a single fixed length communications frame at regular time intervals. 24. An apparatus as recited in claim 23 wherein each said module transmits a receive data packet on each said data in line during said frame synchronized to said clock source and to said start of frame signal. 25. An apparatus as recited in claim 1 wherein said controller communicates with said first module at a first rate of communication and with said second module at a second rate of communication wherein said first rate is different from said second rate, said first rate and said second rates synchronized with said clock source. 26. An apparatus as recited in claim 1 wherein a controller on said module includes JTAG functionality and said controller detects a presence of said module and said module provides an identification code to said controller over said communications link using said JTAG functionality and said controller thereafter configures each said identified module by transmitting a serial data stream using said JTAG functionality. 27. An apparatus as recited in claim 1 wherein each said module has a module processor having JTAG functionality and said data out, data in, and clock lines are connected to a communications port of said module processor and TDI, TDO, and TCK inputs, respectively, of a JTAG port of said module processor through respective isolation elements. 28. An apparatus as recited in claim 27 and further comprising a circuit that generates a TDI window and a TMS window on one of the serial communications link lines to maintain and control test mode select states in a module processor and to transmit JTAG test control (TMS) information while simultaneously using said same serial communications lines to transmit JTAG test input (TDI) data. 29. An apparatus as recited in claim 27 wherein a memory element de-multiplexes and maintains a TMS data stream to TMS of the JTAG port upon and following initial communication with said module over said communications link after a module reset. 30. An apparatus as recited in claim 29 wherein said controller configures said module processor over said communications link using standard JTAG protocols. 31. An apparatus as recited in claim 30 wherein said module processor presets said memory element upon completion of said module processor configuration thereby causing a JTAG "test logic reset" state which terminates JTAG operation while enabling initiation of a different mode of serial communication via the same said data in, data out, and clock lines. 32. An apparatus as recited in claim 1 wherein said controller selectively resets one or more of said modules by selectively forcing respective ones of said clock lines to a consistent state for a predefined amount of time. 33. An apparatus as recited in claim 32 wherein said controller detects, identifies and configures said one or more reset modules. 34. An apparatus comprising: a housing having a controller, a module and a backplane, said backplane distributing power to the module, said backplane also providing a dedicated serial communication link from said controller to said module, said communication link defined as a data out line, a data in line and a clock line, said clock line being derived from a clock source, wherein all connections between said module and said controller through said backplane interconnect through galvanic isolators and wherein said controller transmits send packets over said data out lines synchronized to said clock source and wherein a start of frame signal for each said send packet occurs on a single edge of said clock source and said send data packet contains at least one trigger bit. 35. An apparatus as recited in claim 34 wherein said galvanic isolators are disposed in said module. 36. An apparatus as recited in claim 34 wherein said controller transmits said send packet on said data out line synchronized to said clock source, and said module transmits a receive packet on said data in line synchronized to said clock source wherein said receive packet is delayed from said send packet. 37. An apparatus as recited in claim 36 wherein said send packet is delayed from said receive packet by an integer number of clock cycles. 38. An apparatus as recited in claim 37 wherein said send packet is delayed from said receive packet by two cycles of said clock. 39. An apparatus as recited in claim 36 wherein a first bit for each said receive packet occurs on a single edge of said clock source. 40. An apparatus as recited in claim 34 wherein said at least one trigger bit is received by said module and initiates an operation in said module. 41. An apparatus as recited in claim 34 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a separate action in said module. 42. An apparatus as recited in claim 34 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a same action in said module. 43. An apparatus as recited in claim 34 wherein said controller transmits each said send data packet during a single fixed length communications frame at regular time intervals. 44. An apparatus as recited in claim 43 wherein said module transmits a receive data packet on said data in line during said frame synchronized to said clock source and to said start of frame signal. 45. An apparatus as recited in claim 34 wherein a controller on said module includes JTAG functionality and said controller detects a presence of said module and said module provides an identification code to said controller over said communications link using said JTAG functionality and said controller thereafter configures said identified module by transmitting a serial data stream using said JTAG functionality. 46. An apparatus as recited in claim 34 wherein said module has a module processor having JTAG functionality and said clock, data out, and data in lines are connected to a communications port of said module processor and TCK, TDI and TDO inputs, respectively, of a JTAG port of said module processor through respective isolation elements. 47. An apparatus as recited in claim 46 and further comprising a circuit that generates a TDI window and a TMS window on one of the serial communications link lines to maintain and control test mode select states in a module processor and to transmit JTAG test control (TMS) information while simultaneously using said serial communications link to transmit JTAG test input (TDI) data. 48. An apparatus as recited in claim 46 wherein a memory element de-multiplexes and maintains a TMS data stream to TMS of the JTAG port true upon and following initial communication with said module over said communications link after a module reset. 49. An apparatus as recited in claim 46 wherein said controller configures said module processor over said communications link using standard JTAG protocols. 50. An apparatus as recited in claim 48 wherein said module processor presets said memory element upon completion of said module processor configuration thereby causing a JTAG "test logic reset" state which terminates JTAG operation while enabling initiation of a different mode of serial communication via the same said data in, data out, and clock lines. 51. An apparatus as recited in claim 34 wherein said controller selectively resets one or more of said modules by selectively forcing respective ones of said clock lines to a consistent state for a predefined amount of time. 52. An apparatus as recited in claim 51 wherein said controller detects, identifies and configures said one or more reset modules.
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