Capacitance sensor using relaxation oscillators
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-003/02
H03K-003/00
G01R-027/26
출원번호
US-0273708
(2005-11-14)
등록번호
US-7307485
(2007-12-11)
발명자
/ 주소
Snyder,Warren S.
Ess,David Van
출원인 / 주소
Cypress Semiconductor Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor & Zafman LLP
인용정보
피인용 횟수 :
140인용 특허 :
144
초록▼
An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of
An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of the comparator circuit with hysteresis. The current driver is coupled to the output of the comparator circuit with hysteresis and to the capacitor. The current driver reciprocally sources and sinks a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential. The current driver is responsive to the output of the comparator circuit with hysteresis.
대표청구항▼
What is claimed is: 1. An apparatus, comprising: a comparator circuit with hysteresis including a first input and an output; a capacitor coupled to the first input of the comparator circuit with hysteresis; a current driver coupled to the output of the comparator circuit with hysteresis and to the
What is claimed is: 1. An apparatus, comprising: a comparator circuit with hysteresis including a first input and an output; a capacitor coupled to the first input of the comparator circuit with hysteresis; a current driver coupled to the output of the comparator circuit with hysteresis and to the capacitor, the current driver to reciprocally source and sink a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential responsive to the output of the comparator circuit with hysteresis; a processor coupled to execute instructions; a current source to generate a first reference current; and a scaler unit coupled to receive a digital current control signal from the processor and to selectively scale the first reference current in response to the digital current control signal to generate a second reference current to provide to the current driver. 2. The apparatus of claim 1, wherein a magnitude of the drive current is dependent upon the second reference current. 3. The apparatus of claim 1, wherein the comparator circuit with hysteresis comprises: a flip-flop including first and second inputs and an output, the output of the flip-flop coupled to the current driver; a first comparator including an output coupled to the first input of the flip-flop, a first input coupled to the capacitor, and a second input to receive the high reference potential; and a second comparator including an output coupled to the second input of the flip-flop, a first input coupled to the first input of the first comparator, and a second input to receive the low reference potential. 4. The apparatus of claim 3, wherein the current driver includes: a pull up path coupled between a first voltage rail and the terminal of the capacitor to source the drive current into the terminal of the capacitor, the pull up path responsive to the output of the flip-flop; and a pull down path coupled between a second voltage rail and the terminal of the capacitor to sink the drive current from the terminal of the capacitor, the pull down path responsive to the output of the flip-flop. 5. The apparatus of claim 4, wherein the current driver further includes a current mirror circuit to mirror a reference current into the pull up and pull down paths. 6. The apparatus of claim 5, wherein the pull up path includes first and second positive metal oxide semiconductor ("PMOS") transistors coupled in series, a gate of the first PMOS transistor coupled to the output of the flip-flop, wherein the pull down path includes first and second negative metal oxide semiconductor ("NMOS") transistors coupled in series, a gate of the first NMOS transistor coupled to the output of the flip-flop, wherein the mirror circuit includes a third PMOS transistor coupled between the first voltage rail and a reference current source, the third PMOS transistor having its gate and source coupled to a gate of the second PMOS transistor, and wherein the mirror circuit includes a third NMOS transistor coupled between the second voltage rail and the reference current source, the third NMOS transistor having its gate and drain coupled to a gate of the second NMOS transistor. 7. A method to sense a capacitance, comprising: charging and discharging a reference capacitor with a first drive current generated by a first oscillator oscillating at a first frequency; charging and discharging a device under test ("DUT") capacitor with a second drive current generated by a second oscillator oscillating at a second frequency, wherein the first and second drive currents are scaled from a common reference current; and measuring a capacitance change across the DUT capacitor based on a relative change between the first and second frequencies. 8. The method of claim 7, further comprising: generating a low voltage reference at which the first and second oscillators transition between discharging and charging the reference and DUT capacitors, respectively; and generating a high voltage reference at which the first and second oscillators transition between charging and discharging, the reference and DUT capacitors, respectively. 9. The method of claim 8, further comprising: generating a reference current; and mirroring the reference current into the first and second oscillators to generate the first and second drive currents for charging and discharging the reference capacitor and the DUT capacitor, respectively. 10. The method of claim 8, wherein the low and high voltage references are selectable via a processor. 11. The method of claim 10, wherein the processor is clocked by the first oscillator at the first frequency. 12. The method of claim 8, further comprising: generating a first reference current; mirroring the first reference current into the first oscillator to generate the first drive current for charging and discharging the reference capacitor; generating a second reference current; mirroring the second reference current in the second oscillator to generate the second drive current for charging and discharging the DUT capacitor; adjusting one of the first reference current or the second reference current until the first frequency of the first oscillator matches the second frequency of the second oscillator; and computing the absolute capacitance of the DUT capacitor based at least in part on a current difference between the first and second reference currents when the first and second frequencies match. 13. The method of claim 7, wherein measuring the capacitance change across the DUT capacitor based on the relative change between the first and second frequencies includes: generating a first clock pulse by the first oscillator; dividing a second clock pulse generated by the second oscillator by N to generate N second clock pulses; and counting the number of N second clock pulses that occur during a first clock pulse. 14. A capacitance sensor, comprising: a first oscillator coupled to charge and discharge a reference capacitor with a first drive current at a first frequency, the first oscillator including: a comparator circuit with hysteresis including a first input coupled to the reference capacitor and an output; and a current driver coupled to the output of the comparator circuit with hysteresis and to the reference capacitor, the current driver to reciprocally source and sink the first drive current through a terminal of the reference capacitor to oscillate a voltage potential at the terminal of the reference capacitor between a low reference potential and high reference potential responsive to the output of the comparator circuit with hysteresis; a second oscillator to charge and discharge a device under test ("DUT") capacitor with a second drive current at a second frequency; and a frequency comparator coupled to the first and second oscillators to output a signal indicative of a capacitance change across the DUT capacitor based on a frequency difference between the first and second frequencies. 15. The capacitance sensor of claim 14, further comprising: a voltage source to generate a reference voltage; a voltage scaler coupled to scale the reference voltage to generate a low voltage reference and a high voltage reference, the voltage scaler coupled to provide the low and high voltage references to the first and second oscillators, wherein the first and second oscillators are coupled to oscillate the reference capacitor and the DUT capacitor between the low and high voltage references; a reference current source to generate a first reference current; and a current scaler coupled to scale the first reference current to generate second and third reference currents, wherein the first and second oscillators mirror the second and third reference currents, respectively, to generate the first and second drive currents, respectively. 16. The capacitance sensor of claim 15, further comprising a processor coupled to execute instructions, the processor coupled to the voltage and current scalers to select scaling factors for generating the low and high voltage references and for generating the second and third reference currents. 17. The capacitance sensor of claim 16, wherein the first oscillator is further coupled to provide a clock signal having the first frequency to the processor. 18. The capacitance sensor of claim 14, wherein the frequency comparator includes: a divider circuit coupled to receive a clock signal from the second oscillator having the second frequency and to divide the clock signal by 2N to generate a divided clock signal; and an N-bit register counter coupled to count a number pulses of the divided clock signal that occur during a single pulse of a reference clock signal generated by the first oscillator and having the first frequency. 19. The capacitance sensor of claim 14, wherein the comparator circuit with hysteresis comprises: a flip-flop including first and second inputs and an output, the output of the flip-flop coupled to the current driver; a first comparator including an output coupled to the first input of the flip-flop, a first input coupled to the capacitor, and a second input to receive the high reference potential; and a second comparator including an output coupled to the second input of the flip-flop, a first input coupled to the first input of the first comparator, and a second input to receive the low reference potential. 20. The capacitance sensor of claim 14, wherein the first and second drive currents are each asymmetrical for charging and discharging.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (144)
Cooper Russell E. (Chandler AZ) Ellison Scott (Chandler AZ), Accurate RC oscillator having peak - to - peak voltage control.
Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), Adaptable MOS current mirror.
Steinbach Gnter (Sunnyvale CA) Allen Timothy P. (Los Gatos CA) Mead Carver A. (Pasadena CA), Adaptive analog minimum/maximum selector and subtractor circuit.
Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), CMOS amplifier with offset adaptation.
Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), CMOS current mirror with offset adaptation.
Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), CMOS winner-take all circuit with offset adaptation.
Gerpheide George E. (Salt Lake City UT) Layton Michael D. (Salt Lake City UT), Capacitance-based proximity with interference rejection apparatus and methods.
Platt John C. (Mountain View CA) Wall Michael F. (Sunnyvale CA) Gribble Glenn E. (San Jose CA) Mead Carver A. (Pasadena CA), Circuits for linear conversion between currents and voltages.
Platt John C. (Mountain View CA) Wall Michael F. (Sonnyvale CA) Gribble Glenn E. (San Jose CA) Mead Carver A. (Pasadena CA), Circuits for linear conversion between voltages and currents.
Allen Timothy P. (Los Gatos CA) Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA), Electrically adaptable neural network with post-processing circuitry.
Hatano, Hideki; Yamaji, Takashi; Kitamura, Kenji; Takekawa, Shunji; Nakamura, Masaru, Holographic recording medium and holographic recording/reproducing apparatus using the same.
Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA), Integrating photosensor and imaging system having wide dynamic range with varactors.
Platt John C. (Mountain View CA) Wall Michael F. (Sunnyvale CA) Gribble Glenn E. (San Jose CA) Mead Carver A. (Pasadena CA), Linear, continuous-time, two quadrant multiplier.
Allen Timothy P. (Palo Alto CA) Wall Michael F. (Sunnyvale CA) Faggin Federico (Los Altos Hill CA), Method and apparatus for performing neighborhood operations on a processing plane.
Hino, Takehisa; Koizumi, Yutaka; Kobayashi, Toshiharu; Nakazawa, Shizuo; Harada, Hiroshi; Ishiwata, Yutaka; Yoshioka, Yomei, Nickel-base single-crystal superalloys, method of manufacturing same and gas turbine high temperature parts made thereof.
Miller Robert J. (Fremont CA) Bisset Stephen (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Steinbach Gnter (Palo Alto CA), Object position and proximity detector.
Gillespie David (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Miller Robert J. (Fremont CA) Faggin Federico (Los Altos CA), Object position detector with edge motion feature.
Gillespie David (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Wolf Ralph (Palo Alto CA), Object position detector with edge motion feature and gesture recognition.
Plimon Anton (Graz ATX) Philipp Harald A. (Wegersfeld ATX) Winklhofer Ernst (St. Johann ob Hohenburg/Stmk. ATX), Optoelectronic measuring device for monitoring a combustion chamber.
David T. E. Ely GB; Ross P. Jones GB; James M. C. England GB; Alexander W. McKinnon GB; Robert M. Pettigrew GB; Andrew N. Dames GB; Andrew R. L. Howe GB, Position detector.
Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA) Faggin Federico (Los Altos Hills CA) Anderson Janeen D. W. (Fremont CA), Synaptic element and array.
Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA) Allen Timothy P. (Palo Alto CA) Anderson Janeen D. W. (Femont CA), Synaptic element and array.
Platt John C. (Mountain View) Anderson Janeen D. W. (Fremont) Mead Carver A. (Pasadena CA), Synaptic element including weight-storage and weight-adjustment circuit.
Bisset Stephen (Palo Alto CA) Miller Robert J. (Fremont CA) Allen Timothy P. (Los Gatos CA) Steinbach Gunter (Palo Alto CA 4), Touch pad driven handheld computing device.
Platt John C. (Mountain View CA) Anderson Janeen D. W. (Fremont CA), Two layer neural network comprised of neurons with improved input range and input offset.
Seely Joel ; Malak Robert Leonard ; Allen Timothy Peter ; Schediwy Richard Robert ; Cesarotti William Andrew, Two-layer capacitive touchpad and method of making same.
Allen Timothy P. (Los Gatos CA) Greenblatt Adam K. (San Jose CA) Mead Carver A. (Pasadena CA) Anderson Janeen D. W. (Fremont CA), Writable analog reference voltage storage device.
Allen Timothy P. (Los Gatos CA) Greenblatt Adam K. (San Jose CA) Mead Carver A. (Pasadena CA) Anderson Janeen D. W. (Fremont CA), Writable analog reference voltage storage device.
LeMoncheck John (El Granada CA) Allen Timothy P. (Los Gatos CA) Steinbach Gunter (Palo Alto CA) Mead Carver A. (Pasadena CA), Writable analog reference voltage storage device.
LeMoncheck John (El Granada CA) Allen Timothy P. (Los Gatos CA) Steinbach Gunter (Palo Alto CA) Mead Carver A. (Pasadena CA), Writable analog reference voltage storage device.
Lundstrum, Zeke; Curtis, Keith; Davison, Burke; Steedman, Sean; LeFaou, Yann, Measuring capacitance of a capacitive sensor with a microcontroller having an analog output for driving a guard ring.
Lundstrum, Zeke; Curtis, Keith; Davison, Burke; Steedman, Sean; LeFaou, Yann, Measuring capacitance of a capacitive sensor with a microcontroller having digital outputs for driving a guard ring.
McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.