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Iterative decoder employing multiple external code error checks to lower the error floor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03M-013/03
  • H03M-013/00
출원번호 US-0892738 (2004-07-16)
등록번호 US-7310768 (2007-12-18)
발명자 / 주소
  • Eidson,Donald Brian
  • Krieger,Abraham
  • Murali,Ramaswamy
출원인 / 주소
  • Conexant Systems, Inc.
대리인 / 주소
    Howrey LLP
인용정보 피인용 횟수 : 176  인용 특허 : 5

초록

Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performanc

대표청구항

What is claimed is: 1. An iterative decoder, comprising: an internal code decoder operable to perform iterative decoding of a data block; and an external code decoder capable of supplying a feedback signal to the internal decoder wherein the feedback signal is used to influence selective decisions

이 특허에 인용된 특허 (5)

  1. Joachim Hagenauer DE; Rupert Herzog DE; Andreas Schmidbauer DE, Decoding method and decoding device for a CDMA transmission system for demodulating a received signal available in serial code concatenation.
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  5. Hladik Stephen Michael ; Ross John Anderson Fergus ; Van Stralen Nick Andrew, Turbo code decoder with modified systematic symbol transition probabilities.

이 특허를 인용한 특허 (176)

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