Method for efficient inter-processor communication in an active-active RAID system using PCI-express links
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-013/24
G06F-013/20
G06F-013/00
출원번호
US-0178727
(2005-07-11)
등록번호
US-7315911
(2008-01-01)
발명자
/ 주소
Davies,Ian Robert
Maine,Gene
Vedder,Rex Weldon
출원인 / 주소
Dot Hill Systems Corporation
대리인 / 주소
Davis,E. Alan
인용정보
피인용 횟수 :
79인용 특허 :
35
초록▼
A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the h
A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.
대표청구항▼
We claim: 1. A method for a first redundant array of inexpensive disks (RAID) controller to transfer data to a second RAID controller over a PCI-Express link via a PCI-Express memory write request transaction layer packet (TLP) and to also communicate an interrupt request to a processor of the seco
We claim: 1. A method for a first redundant array of inexpensive disks (RAID) controller to transfer data to a second RAID controller over a PCI-Express link via a PCI-Express memory write request transaction layer packet (TLP) and to also communicate an interrupt request to a processor of the second RAID controller via the address field of the header of the TLP, the method comprising: receiving the memory write request TLP, by a PCI-Express controller of the second RAID controller, from the first RAID controller via the PCI-Express link; interpreting, by the PCI-Express controller, a predetermined address bit of the address field of the TLP header as an interrupt request flag rather than as an address bit; determining, by the PCI-Express controller, whether the interrupt request flag is a predetermined value; and interrupting the processor, by the PCI-Express controller, if the interrupt request flag is the predetermined value. 2. The method of claim 1, further comprising: refraining from interrupting the processor, by the PCI-Express controller, if the interrupt request flag is other than the predetermined value. 3. The method of claim 1, further comprising: writing, by the PCI-Express controller, the data of the TLP into a memory of the second RAID controller at a location specified by an address in the address field, wherein the address excludes the predetermined bit. 4. The method of claim 1, further comprising: transmitting, by the PCI-Express controller, a second memory write request TLP to the first RAID controller via the PCI-Express link, for acknowledging receipt of the first memory write request TLP. 5. The method of claim 4, further comprising: receiving the second memory write request TLP, by a PCI-Express controller of the first RAID controller, from the second RAID controller via the PCI-Express link; interpreting, by the PCI-Express controller of the first RAID controller, the predetermined address bit of the address field of the TLP header as the interrupt request flag rather than as an address bit; determining, by the PCI-Express controller of the first RAID controller, whether the interrupt request flag is the predetermined value; and interrupting a processor of the first RAID controller, by the PCI-Express controller of the first RAID controller, if the interrupt request flag is the predetermined value. 6. The method of claim 1, wherein the PCI-Express memory write request TLP has a 4 double word header with data format, wherein the predetermined bit is bit 63 of the address field. 7. The method of claim 1, wherein the PCI-Express memory write request TLP has a 4 double word header with data format, wherein the predetermined bit is one of bits 63 through 32 of the address field. 8. The method of claim 1, wherein the PCI-Express memory write request TLP has a 3 double word header with data format, wherein the predetermined bit is bit 31 of the address field. 9. The method of claim 1, wherein the PCI-Express memory write request TLP has a 3 double word header with data format, wherein the predetermined bit is one of bits 31 through 16 of the address field. 10. The method of claim 1, wherein the first and second RAID controllers operate as an active-active redundant pair. 11. The method of claim 1, further comprising: interpreting, by the PCI-Express controller, a predetermined plurality of address bits of the address field of the TLP header as a message tag rather than as address bits, wherein a value of the message tag indicates one of a plurality of message buffers of the second RAID controller, wherein the TLP data is a message; writing, by the PCI-Express controller, the message into the one of the plurality of message buffers indicated by the message tag value; and updating a register of the PCI-Express controller to indicate the one of the plurality of message buffers specified by the message tag value, prior to said interrupting the processor. 12. The method of claim 11, wherein the predetermined address bit and the predetermined plurality of address bits are mutually exclusive. 13. The method of claim 11, wherein said writing by the PCI-Express controller the message into the one of the plurality of message buffers comprises writing the message into a memory of the second RAID controller at a location specified by an address in the address field, wherein the address excludes the predetermined bit and the predetermined plurality of bits. 14. The method of claim 11, wherein the plurality of message buffers are comprised in a first memory of the second RAID controller distinct from a second memory of the second RAID controller, wherein the second memory is directly coupled to the processor for storing program instructions executed by the processor. 15. The method of claim 11, further comprising: reading the register, by the processor, after said updating the register, to determine the one of the plurality of message buffers into which the message was written. 16. The method of claim 11, further comprising: transmitting, by the PCI-Express controller, a second memory write request TLP to the first RAID controller via the PCI-Express link, after said interrupting the processor, for acknowledging receipt of the first memory write request TLP. 17. The method of claim 16, further comprising: receiving a plurality of memory write request TLPs, by the PCI-Express controller, from the first RAID controller via the PCI-Express link, prior to said transmitting by the PCI-Express controller the second memory write request TLP for acknowledging receipt of the first memory write request TLP, wherein each of the plurality of memory write request TLPs has a unique value of the message tag. 18. The method of claim 17, further comprising: writing, by the PCI-Express controller, the message of each of the plurality of memory write request TLPs into a plurality of the plurality of message buffers indicated by the message tag value of each of the respective plurality of memory write request TLPs. 19. The method of claim 18, further comprising: updating the register to indicate each of the plurality of the plurality of message buffers specified by the message tag values. 20. The method of claim 19, further comprising: reading the register, by the processor, after said updating the register to indicate each of the plurality of the plurality of message buffers specified by the message tag values, to determine each of the plurality of the plurality of message buffers into which the messages were written. 21. The method of claim 20, further comprising: transmitting, by the PCI-Express controller, a second plurality of memory write request TLPs to the first RAID controller via the PCI-Express link, for acknowledging receipt of the first plurality of memory write request TLPs. 22. The method of claim 11, wherein the message comprises a heartbeat for informing the second RAID controller that the first RAID controller is operating properly. 23. The method of claim 11, wherein the message comprises information specifying a configuration of storage devices coupled to and controlled by the first RAID controller. 24. The method of claim 11, wherein the message comprises a command from the first RAID controller to the second RAID controller to begin a failback operation. 25. The method of claim 11, wherein the message comprises a command from the first RAID controller to the second RAID controller to temporarily pause I/O operations with storage devices coupled to and controlled by the second RAID controller. 26. The method of claim 11, wherein the message comprises a command from the first RAID controller to the second RAID controller to resume I/O operations with storage devices coupled to and controlled by the second RAID controller. 27. The method of claim 11, wherein the message comprises a command from the first RAID controller to the second RAID controller to reboot. 28. The method of claim 11, wherein the message comprises a command from the first RAID controller to the second RAID controller to synchronize a cache memory of the second RAID controller with storage devices coupled to and controlled by the second RAID controller. 29. The method of claim 11, wherein the message comprises a command from the first RAID controller to the second RAID controller to refresh information specifying a configuration of storage devices coupled to and controlled by the RAID controllers. 30. The method of claim 11, wherein the message comprises a message to notify the second RAID controller of an event occurring on an I/O interface of the first RAID controller. 31. The method of claim 11, wherein the message comprises information indicating one or more cache memory locations of the second RAID controller into which the first RAID controller will subsequently transfer mirrored write cache data. 32. The method of claim 31, further comprising: clearing valid indicators, by the second RAID controller, associated with each of the cache memory locations, in response to the message, before the first RAID controller transfers the mirrored write cache data. 33. The method of claim 32, further comprising: transferring, by the first RAID controller, the mirrored write cache data to the second RAID controller in one or more TLPs via the PCI-Express link, after said clearing the valid indicators. 34. The method of claim 33, further comprising: setting valid indicators, by the second RAID controller, associated with each of the cache memory locations, after said transferring the mirrored write cache data. 35. The method of claim 11, wherein the message comprises information indicating one or more memory locations of the second RAID controller into which the first RAID controller will subsequently transfer data. 36. The method of claim 35, wherein the data comprises RAID data log information. 37. The method of claim 35, wherein the data comprises user input information. 38. The method of claim 11, wherein the PCI-Express memory write request TLP has a 4 double word header with data format, wherein the predetermined plurality of bits is a plurality of bits 63 through 32 of the address field. 39. The method of claim 11, wherein the PCI-Express memory write request TLP has a 3 double word header with data format, wherein the predetermined plurality of bits is a plurality of bits 31 through 16 of the address field. 40. The method of claim 1, further comprising: programming, by a processor of the first RAID controller, a PCI-Express controller of the first RAID controller to transmit the memory write request TLP to the second RAID controller via the PCI-Express link. 41. The method of claim 40, wherein said programming comprises: providing a scatter/gather list of entries specifying data to be transferred to the second RAID controller via the PCI-Express link, wherein the memory write request TLP contains data specified by one of the scatter/gather list entries. 42. The method of claim 41, wherein the scatter/gather list entries indicate whether or not to set the interrupt request flag to the predetermined value. 43. A system wherein processors of redundant array of inexpensive disks (RAID) controllers communicate via a PCI-Express link using a PCI-Express memory write request transaction layer packet (TLP) having an address field within a header of the TLP, the system comprising: a PCI-Express link; a first RAID controller, having a first PCI-Express controller coupled to said PCI-Express link, and a first processor configured to cause said first PCI-Express controller to transmit on said PCI-Express link a PCI-Express memory write request TLP, wherein said processor is configured to cause said first PCI-Express controller to selectively set a predetermined address bit of the address field of the TLP header to a predetermined value as an interrupt request flag rather than as an address bit; and a second RAID controller, having a second processor, and a second PCI-Express controller coupled to said PCI-Express link, configured to receive the TLP from said first RAID controller, and to interrupt said second processor if said interrupt request flag is said predetermined value. 44. The system of claim 43, wherein each of said first and second RAID controllers further comprises: a memory, coupled to said PCI-Express controller; wherein said second PCI-Express controller is configured to write the data of the TLP into said memory of said second RAID controller at a location specified by an address in the address field, wherein said address excludes the predetermined bit. 45. The system of claim 43, wherein the PCI-Express memory write request TLP has a 4 double word header with data format, wherein said predetermined bit is bit 63 of the address field. 46. The system of claim 43, wherein the PCI-Express memory write request TLP has a 4 double word header with data format, wherein said predetermined bit is one of bits 63 through 32 of the address field. 47. The system of claim 43, wherein the PCI-Express memory write request TLP has a 3 double word header with data format, wherein said predetermined bit is bit 31 of the address field. 48. The system of claim 43, wherein the PCI-Express memory write request TLP has a 3 double word header with data format, wherein said predetermined bit is one of bits 31 through 16 of the address field. 49. The system of claim 43, wherein said second PCI-Express controller is further configured to interpret a predetermined plurality of address bits of the address field of the TLP header as a message tag rather than as address bits, wherein a value of said message tag indicates one of a plurality of message buffers of said second RAID controller, wherein the TLP data is a message, wherein said second PCI-Express controller is further configured to write said message into said one of said plurality of message buffers indicated by said message tag value, wherein said second PCI-Express controller is further configured to update a register to indicate said one of said plurality of message buffers specified by said message tag value, prior to interrupting the processor. 50. The system of claim 49, wherein said second PCI-Express controller writes the message into a memory of said second RAID controller at a location specified by an address in the address field, wherein said address excludes the predetermined bit and the predetermined plurality of bits. 51. The system of claim 49, wherein said second processor is configured to read said register, after updating said register, to determine said one of said plurality of message buffers into which said message was written. 52. The system of claim 51, wherein said second PCI-Express controller is further configured to receive a plurality of memory write request TLPs from said first RAID controller via said PCI-Express link, prior to transmitting a second memory write request TLP for acknowledging receipt of said first memory write request TLP, wherein each of said plurality of memory write request TLPs has a unique value of said message tag. 53. The system of claim 52, wherein said second PCI-Express controller is further configured to update said register to indicate each of said plurality of said plurality of message buffers specified by said message tag values. 54. The system of claim 53, wherein said second processor is further configured to read said register, after updating said register, to determine each of said plurality of said plurality of message buffers into which said messages were written. 55. The system of claim 49, wherein the message comprises a command from said first RAID controller to said second RAID controller to begin a failback operation. 56. The system of claim 49, wherein said message comprises information indicating one or more cache memory locations of said second RAID controller into which said first RAID controller will subsequently transfer mirrored write cache data. 57. The system of claim 56, wherein said second RAID controller is configured to clear valid indicators associated with each of said cache memory locations, in response to said message, before said first RAID controller transfers said mirrored write cache data. 58. The system of claim 57, wherein said second RAID controller is further configured to set said valid indicators after transferring said mirrored write cache data. 59. The system of claim 49, wherein the PCI-Express memory write request TLP has a 4 double word header with data format, wherein said predetermined plurality of bits is a plurality of bits 63 through 32 of the address field. 60. The system of claim 49, wherein the PCI-Express memory write request TLP has a 3 double word header with data format, wherein said predetermined plurality of bits is a plurality of bits 31 through 16 of the address field. 61. The system of claim 43, wherein said first processor is configured to program said first PCI-Express controller to transmit said memory write request TLP to said second RAID controller via said PCI-Express link. 62. A method for a first redundant array of inexpensive disks (RAID) controller to transfer data to a second RAID controller over a PCI-Express link via a PCI-Express memory write request transaction layer packet (TLP) and to also communicate an interrupt request to a processor of the second RAID controller via the header of the TLP, the method comprising: receiving the memory write request TLP, by a PCI-Express controller of the second RAID controller, from the first RAID controller via the PCI-Express link; interpreting, by the PCI-Express controller, a predetermined unused bit of the TLP header as an interrupt request flag rather than as the bit's standard function specified in the PCI-Express specification; writing, by the PCI-Express controller, payload data of the TLP into a memory of the second RAID controller at a location specified by an address in the TLP header; determining, by the PCI-Express controller, whether the interrupt request flag is a predetermined value; and interrupting the processor, by the PCI-Express controller, if the interrupt request flag is the predetermined value. 63. The method of claim 62, wherein the unused bit comprises one of the Traffic Class (TC) bits specified by the PCI-Express specification. 64. The method of claim 62, wherein the unused bit comprises the TLP Digest (TD) bit specified by the PCI-Express specification. 65. The method of claim 62, wherein the unused bit comprises the data poisoning (EP) bit specified by the PCI-Express specification. 66. The method of claim 62, wherein the unused bit comprises one of the Transaction Descriptor Attributes field bits specified by the PCI-Express specification. 67. The method of claim 62, wherein the unused bit comprises one of the bits of the tag field of the transaction ID specified by the PCI-Express specification. 68. The method of claim 62, wherein the unused bit comprises one of the bits of the function number field of the transaction ID specified by the PCI-Express specification. 69. The method of claim 62, wherein the unused bit comprises one of the byte enable field bits specified by the PCI-Express specification. 70. The method of claim 62, further comprising: interpreting, by the PCI-Express controller, a predetermined unused plurality of bits of the TLP header as a message tag rather than as the bits' standard function specified in the PCI-Express specification, wherein a value of the message tag indicates one of a plurality of message buffers of the second RAID controller, wherein the TLP data is a message; writing, by the PCI-Express controller, the message into the one of the plurality of message buffers indicated by the message tag value; and updating a register of the PCI-Express controller to indicate the one of the plurality of message buffers specified by the message tag value, prior to said interrupting the processor. 71. The method of claim 70, wherein the unused plurality of bits comprise a plurality of the bits Reserved by the PCI-Express specification. 72. The method of claim 70, wherein the unused plurality of bits comprise a plurality of the Traffic Class (TC) bits specified by the PCI-Express specification. 73. The method of claim 70, wherein the unused plurality of bits comprise the Transaction Descriptor Attributes field bits specified by the PCI-Express specification. 74. The method of claim 70, wherein the unused plurality of bits comprise a plurality of the bits of the tag field of the transaction ID specified by the PCI-Express specification. 75. The method of claim 70, wherein the unused plurality of bits comprise a plurality of the bits of the function number field of the transaction ID specified by the PCI-Express specification. 76. The method of claim 70, wherein the unused plurality of bits comprise a plurality of the byte enable field bits specified by the PCI-Express specification. 77. The method of claim 62, wherein the unused bit comprises a bit Reserved by the PCI-Express specification. 78. A system wherein processors of redundant array of inexpensive disks (RAID) controllers transfer data with one another via a PCI-Express link using a PCI-Express memory write request transaction layer packet (TLP) and also communicate an interrupt request to each other via a header of the TLP, the system comprising: a PCI-Express link; a first RAID controller, having a first PCI-Express controller coupled to said PCI-Express link, and a first processor configured to cause said first PCI-Express controller to transmit on said PCI-Express link a PCI-Express memory write request TLP, wherein said processor is configured to cause said first PCI-Express controller to selectively set a predetermined unused bit of the TLP header to a predetermined value for use as an interrupt request flag rather than as the bit's standard function specified in the PCI-Express specification; and a second RAID controller, having a second processor, and a second PCI-Express controller coupled to said PCI-Express link, configured to receive the TLP from said first RAID controller, to write payload data of the TLP into a memory of said second RAID controller at a location specified by an address in the TLP header, and to interrupt said second processor if said interrupt request flag is said predetermined value. 79. The system of claim 78, wherein said second RAID controller further comprises: a plurality of message buffers, coupled to said second processor, for storing a plurality of messages received on said PCI-Express link from said first RAID controller; and a register, coupled to said second processor, for storing an indication of which of said plurality of message buffers contains a valid message. 80. The system of claim 79, wherein said second PCI-Express controller is configured to interpret a predetermined unused plurality of bits of the TLP header as a message tag rather than as said bits' standard function specified in the PCI-Express specification, wherein a value of the message tag indicates one of said plurality of message buffers. 81. The system of claim 80, wherein in response to receiving said TLP, if said interrupt request flag is said predetermined value, said second PCI-Express controller is configured to update said register to indicate said one of said plurality of message buffers specified by said message tag value, prior to interrupting said processor. 82. The system of claim 81, wherein said TLP contains a message, wherein said second PCI-Express controller is configured to write said message into said one of said plurality of message buffers indicated by said message tag value, prior to interrupting said processor.
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이 특허에 인용된 특허 (35)
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Flanagan, John R.; Casper, Daniel F.; Kalos, Matthew J.; Riedy, Dale F.; Sittmann, Gustav E.; Njoku, Ugochukwu C.; Huang, Catherine C., Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system.
Flanagan, John R.; Casper, Daniel F.; Kalos, Matthew J.; Riedy, Dale F.; Sittmann, Gustav E.; Njoku, Ugochukwu C.; Huang, Catherine C., Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system.
Casper, Daniel F.; Bendyk, Mark P.; Flanagan, John R.; Huang, Catherine C.; Kalos, Matthew J.; Njoku, Ugochukwu C.; Riedy, Dale F.; Sittmann, Gustav E.; Yudenfriend, Harry M., Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous.
Casper, Daniel F.; Bendyk, Mark P.; Flanagan, John R.; Huang, Catherine C.; Kalos, Matthew J.; Njoku, Ugochukwu C.; Riedy, Dale F.; Sittmann, III, Gustav E.; Yudenfriend, Harry M., Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous.
Casper, Daniel F.; Bendyk, Mark P.; Flanagan, John R.; Huang, Catherine C.; Kalos, Matthew J.; Njoku, Ugochukwu C.; Riedy, Dale F.; Sittmann, III, Gustav E.; Yudenfriend, Harry M., Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous.
Biran, Giora; Granovsky, Ilya; Perlin, Elchanan, System and method for a credit based flow device that utilizes PCI express packets having modified headers wherein ID fields includes non-ID data.
Casper, Daniel F.; Flanagan, John R., System and program products for facilitating access to status and measurement data associated with input/output processing.
Casper, Daniel F.; Flanagan, John R., System and program products for facilitating input/output processing by using transport control words to reduce input/output communications.
Carlson, Scott M.; Casper, Daniel F.; Flanagan, John R.; Hathorn, Roger G.; Kalos, Matthew J.; Ricci, Louis W.; Sittman, III, Gustav E., Transport mode data transfer between a channel subsystem and input/output devices.
Carlson, Scott M.; Casper, Daniel F.; Flanagan, John R.; Hathorn, Roger G.; Kalos, Matthew J.; Ricci, Louis W.; Sittmann, III, Gustav E., Transport mode data transfer between a channel subsystem and input/output devices.
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