초록 ▼

Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum numbe

Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign-or unsigned-extended when transferred.

대표청구항 ▼

The invention claimed is: 1. A data processing system comprising: a memory for storing operands; a plurality of general purpose registers wherein each general purpose register holds multiple data elements; and processor circuitry for executing one or more instructions, at least one of the one or mo

The invention claimed is: 1. A data processing system comprising: a memory for storing operands; a plurality of general purpose registers wherein each general purpose register holds multiple data elements; and processor circuitry for executing one or more instructions, at least one of the one or more instructions for transferring a plurality of data elements between the memory and the at least two of the plurality of general purpose registers wherein the at least one or more instructions specifies a number of data elements to be transferred between each of the at least two of the plurality of general purpose registers and the memory, wherein the at least one of the one or more instructions provides a first offset between data elements within a first portion of successive data elements to be stored into the memory or loaded from the memory and a second offset between a first portion and a second portion of the data elements to be stored into the memory or loaded from the memory. 2. The data processing system of claim 1 wherein the one or more instructions additionally specifies which of the data elements to load or store in addition to the number of data elements to be transferred. 3. The data processing system of claim 1 wherein when only a subset of the multiple data elements is transferred between each of the at least two of the plurality of general purpose registers and the memory, any unspecified data elements are filled with a predetermined value. 4. The data processing system of claim 3 wherein the predetermined value comprises a zero value having all bits equal to zero. 5. The data processing system of claim 1, wherein the number of data elements specified by the at least one or more instructions specifies only a subset of the multiple data elements in each of the at least two general purpose registers to be transferred. 6. A method of transferring data elements in a data processing system comprising: storing operands in a memory; storing multiple data elements in each of a plurality of general purpose registers; and executing one or more instructions in the data processing system, at least one of the one or more instructions causing a transfer of a plurality of data elements between the memory and the at least two of the plurality of general purpose registers, wherein the at least one or more instructions specifies a number of data elements to be transferred between each of the at least two of the plurality of general purpose registers and the memory, wherein the at least one of the one or more instructions provides a first offset between data elements within a first portion of successive data elements to be stored into the memory or loaded from the memory and a second offset between a first portion and a second portion of the data elements to be stored into the memory or loaded from the memory. 7. The method of claim 6 further comprising: specifying with each of the one or more instructions which of the data elements to load or store in addition to the number of data elements to be transferred. 8. The method of claim 6 further comprising: when only a subset of the multiple data elements is transferred between each of the at least two of the plurality of general purpose registers and the memory, filling any unspecified data elements with a predetermined value. 9. A data processing system comprising: a memory for storing operands; a plurality of general purpose registers wherein each general purpose register holds multiple data elements; and processor circuitry for executing one or more instructions, at least one of the one or more instructions for transferring a plurality of data elements between the memory and the at least two of the plurality of general purpose registers wherein the at least one or more instructions specifies which subset of the multiple data elements in each of the at least two of the plurality of general purpose registers are to be transferred, wherein the at least one of the one or more instructions provides a first offset between data elements within a first portion of successive data elements to be stored into the memory or loaded from the memory and a second offset between a first portion and a second portion of the data elements to be stored into the memory or loaded from the memory. 10. The data processing system of claim 9 wherein, any unspecified data elements are filled by the processor circuitry with a predetermined value. 11. The data processing system of claim 10 wherein the predetermined value is a zero value. 12. The data processing system of claim 9 wherein the subset of the multiple data elements specified by the at least one or more instructions are contiguously positioned within the at least two of the plurality of general purpose registers. 13. The data processing system of claim 9 wherein the subset of the multiple data elements specified by the at least one or more instructions are not contiguously positioned within the at least two of the plurality of general purpose registers. 14. A method of transferring data elements in a data processing system comprising: storing operands in a memory; holding multiple data elements in each of a plurality of general purpose registers; and executing one or more instructions, at least one of the one or more instructions causing a transfer of a plurality of data elements between the memory and at least two of the plurality of general purpose registers wherein the at least one or more instructions specifies which subset of the multiple data elements in each of the at least two of the plurality of general purpose registers are to be transferred, wherein the at least one of the one or more instructions provides a first offset between data elements within a first portion of successive data elements to be stored into the memory or loaded from the memory and a second offset between a first portion and a second portion of the data elements to be stored into the memory or loaded from the memory. 15. The method of claim 14 further comprising filling any unspecified data elements with a predetermined value. 16. A data processing system comprising: a memory for storing operands; a plurality of general purpose registers wherein each general purpose register holds multiple data elements; and processor circuitry for executing one or more instructions, at least one of the one or more instructions for transferring a plurality of data elements between the memory and the at least two of the plurality of general purpose registers wherein the at least one or more instructions specifies both a number of data elements to be transferred between each of the at least two of the plurality of general purpose registers and the memory and further specifies a total number of data elements to be transferred, wherein the at least one of the one or more instructions provides a first offset between data elements within a first portion of successive data elements to be stored into the memory or loaded from the memory and a second offset between a first portion and a second portion of the data elements to be stored into the memory or loaded from the memory. 17. The data processing system of claim 16 wherein when a total number of data elements to be transferred is greater than a number of data elements to be transferred to each of the at least two of the plurality of general purpose registers, data elements are transferred to a predetermined one of the plurality of general purpose registers. 18. The data processing system of claim 16 wherein when a total number of data elements to be transferred is less than a number of data elements to be transferred to each of the at least two of the plurality of general purpose registers, any remaining specified data elements of the plurality of general purpose registers are filled with a predetermined value. 19. The data processing system of claim 18 wherein the predetermined value is a zero value. 20. The data processing system of claim 16 wherein the one or more instructions specifies by using a field in the instruction to identify the number of data elements to be transferred between each of the at least two of the plurality of general purpose registers and the memory and to identify the total number of data elements to be transferred. 21. The data processing system of claim 16 wherein the one or more instructions specifies by identifying a register within the data processing system that contains information to identify the number of data elements to be transferred between each of the at least two of the plurality of general purpose registers and the memory and to identify the total number of data elements to be transferred. 22. The data processing system of claim 16 wherein the data elements are positioned in contiguous storage locations in the memory. 23. The data processing system of claim 16 wherein the data elements are positioned in non-contiguous storage locations in the memory.