초록 ▼

A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the

A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.

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What is claimed is: 1. A method for fabricating elevated bond pads on semiconductor chips comprising the steps of: providing a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads, said top metal pads in recesses and planar with a first insulating

What is claimed is: 1. A method for fabricating elevated bond pads on semiconductor chips comprising the steps of: providing a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads, said top metal pads in recesses and planar with a first insulating layer on said substrate; forming a second insulating layer over said top metal pads and with openings to top surface of said top metal pads; forming elevated bond pads in said openings and extending above surface of said second insulating layer, with exposed sidewalls on said elevated bond pads; forming sidewall spacers on said exposed sidewalls; and forming an under-bump material barrier layer selectively on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu. 2. The method of claim 1, wherein said semiconductor chips have integrated circuits (devices) electrically connected to said top metal pads. 3. The method of claim 1, wherein said top metal pads are formed by depositing a conformal barrier layer of Ta/TaN and filling said recesses with copper. 4. The method of claim 1, wherein said second insulating layer is a dual-layer of silicon oxide and silicon nitride or a tri-layer of silicon oxide-silicon nitride-silicon oxide and is deposited to a thickness of between 1000 and 20000 Angstroms. 5. The method of claim 1, wherein said elevated bond pads are formed by: depositing a conformal Ta/TaN barrier layer and anisotropically etching back to leave said Ta/TaN barrier layer on the sidewalls of said openings while exposing the top surface of said second insulating layer and top surface of said top metal pads in said openings; and electroless plating copper selectively in said openings, and said elevated bond pads have a height of at least greater than 800 Angstroms above top surface of said second insulating layer. 6. The method of claim 1, wherein said sidewalls spacers are formed by depositing a conformal insulating layer of silicon oxide or silicon nitride formed to a thickness of between about 100 and 1000 Angstroms, and anisotropically etching back said insulating layer to top surface of said elevated bond pads. 7. The method of claim 1, wherein said under-bump material barrier layer is deposited and patterned using a photoresist mask to leave portions on top surface of said elevated bond pads. 8. A method for fabricating elevated bond pads on semiconductor chips comprising the steps of: providing a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads in recesses and planar with a first insulating layer on said substrate; forming a second insulating layer over said top metal pads and with openings to top surface of said top metal pads; depositing a conformal barrier layer and an electrically conducting layer and patterning to form elevated bond pads in and aligned over said openings and extending above the surface of said second insulating layer with exposed first sidewalls on said elevated bond pads; patterning said elevated bond pads by partial anisotropically etching to further reduce the top surface area and form second sidewalls on said elevated bond pads; forming sidewall spacers on said exposed first and second sidewalls; and forming an under-bump material barrier layer selectively on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu. 9. The method of claim 8, wherein said semiconductor chips have integrated circuits (devices) electrically connected to said top metal pads. 10. The method of claim 8, wherein said top metal pads are formed by depositing a conformal barrier layer of Ta/TaN and filling said recesses with copper. 11. The method of claim 8, wherein said second insulating layer is a dual-layer of silicon oxide and silicon nitride or a tri-layer of silicon oxide-silicon nitride-silicon oxide and is deposited to a thickness of between 1000 and 20000 Angstroms. 12. The method of claim 8, wherein said elevated bond pads are formed by: depositing a conformal Ta/TaN barrier layer and depositing an aluminum alloy to fill said openings; using a first photoresist mask and anisotropically etching to form said elevated bond pads over said openings and to form said first sidewalls on said elevated bond pads; and using a second photoresist mask and partially anisotropically etching to reduce the top surface of said elevated bond pads and to form said second sidewalls on said elevated bond pads, and said elevated bond pads have a height of at least greater than 800 Angstroms above the top surface of said second insulating layer. 13. The method of claim 8, wherein said sidewall spacers are formed by depositing a conformal insulating layer of silicon oxide or silicon nitride formed to a thickness of between about 100 and 1000 Angstroms, and anisotropically etching back to top surface of said elevated bond pads. 14. The method of claim 8, wherein said under-bump material barrier layer is deposited and patterned using a photoresist mask to leave portions on the top surface of said elevated bond pads. 15. Elevated bond-pads on semiconductor chips comprised of: a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads, said metal pads in recesses and planar with a first insulating layer on said substrate; a second insulating layer over said top metal pads and with openings to top surface of said top metal pads; said elevated bond pads in said openings and extending above the surface of said second insulating layer, with sidewalls on said elevated bond pads; sidewall spacers on said sidewalls; and an under-bump material barrier layer on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and, Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu. 16. The structure of claim 15, wherein said second insulating layer is a dual-layer of silicon oxide and silicon nitride or a tri-layer of silicon oxide SiN/SiO2 and has a thickness of between 1000 and 20000 Angstrom. 17. The structure of claim 15, wherein said elevated bond pads are copper formed by electroless plating and have a height of at least greater than 800 Angstroms above the top surface of said second insulating layer. 18. The structure of claim 15, wherein said elevated bond pads are an aluminum alloy and have a height of at least greater than 800 Angstroms above the top surface of the second insulating layer and said elevated bond pads are recessed and have second sidewalls on said elevated bond pads to reduce the top surface areas of said elevated bond pads, and wherein said sidewall spacers are silicon oxide or silicon nitride.