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Method for compensated sensing in non-volatile memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0321681 (2005-12-28)
등록번호 US-7324393 (2008-01-29)
발명자 / 주소
  • Chan,Siu Lung
  • Cernea,Raul Adrian
출원인 / 주소
  • Sandisk Corporation
대리인 / 주소
    Davis Wright Tremaine LLP
인용정보 피인용 횟수 : 47  인용 특허 : 66

초록

One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier s

대표청구항

The invention claimed is: 1. A method of sensing a current relative to a reference current, comprising: providing a sensing circuit for sensing the current, said sensing circuit sensing over a predetermined period to produce either first or second signal depending respectively on whether the sensed

이 특허에 인용된 특허 (66)

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이 특허를 인용한 특허 (47)

  1. Cernea, Raul Adrian; Scheuerlein, Roy E., 3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof.
  2. Cernea, Raul Adrian; Chen, Yung-Tin; Samachisa, George, 3D non-volatile memory having low-current cells and methods.
  3. Scheuerlein, Roy E., Continuous mesh three dimensional non-volatile storage with vertical select devices.
  4. Scheuerlein, Roy E., Continuous mesh three dimensional non-volatile storage with vertical select devices.
  5. Scheuerlein, Roy E., Continuous mesh three dimensional non-volatile storage with vertical select devices.
  6. Petti, Christopher J., Interleaved grouped word lines for three dimensional non-volatile storage.
  7. Chien, Henry; Lee, Yao-Sheng; Samachisa, George; Alsmeier, Johann, Memories with cylindrical read/write stacks.
  8. Cernea, Raul Adrian; Chien, Henry, Method for forming staircase word lines in a 3D non-volatile memory having vertical bit lines.
  9. Samachisa, George; Fasoli, Luca; Higashitani, Masaaki; Scheuerlein, Roy Edwin, Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines.
  10. Yan, Tianhong; Scheuerlein, Roy Edwin, Non-volatile 3D memory with cell-selectable word line decoding.
  11. Cernea, Raul Adrian, Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof.
  12. Cernea, Raul Adrian; Samachisa, George, Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof.
  13. Samachisa, George; Fasoli, Luca; Li, Yan; Yan, Tianhong, Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof.
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  18. Samachisa, George; Alsmeier, Johann, Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof.
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  35. Samachisa, George, Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture.
  36. Yan, Tianhong; Samachisa, George, Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture.
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  39. Rabkin, Peter; Higashitani, Masaaki, Vertical bit line TFT decoder for high voltage operation.
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