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A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously app

A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register.

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I claim: 1. A configurable address buffer system operable to receive at least one set of address signals and output an address, the system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output

I claim: 1. A configurable address buffer system operable to receive at least one set of address signals and output an address, the system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing one set of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing two sets of the address signals; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 2. The system of claim 1 wherein the address signals are coupled to the configurable address buffer through a bus, and wherein the address configuration selector is operable to develop the control signal as a function of a width of the bus. 3. The system of claim 2 wherein the control signal is indicative of the first addressing configuration when the bus has a first width and the second addressing configuration when the bus has a second width. 4. The system of claim 1, the configurable address buffer system operable to utilize a clock signal, and wherein the address signals in each of the sets in the second number are each received during successive clock periods. 5. The system of claim 1, the configurable address buffer system operable to utilize a clock signal, and wherein the address signals in each of the sets in the second number are received at successive clock transitions. 6. The system of claim 1 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 7. The system of claim 1 wherein the address configuration selector comprises a mode register. 8. The system of claim 1 wherein the address configuration selector comprises fuses. 9. The system of claim 1 wherein the address configuration selector comprises anti-fuses. 10. The system of claim 1 wherein the address configuration selector comprises an externally applied mode select signal. 11. A memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to utilize a clock signal and to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals, the address signals in each of the sets in the second number being received during successive clock periods; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 12. The memory device of claim 11 wherein the addressable array of memory cells are arranged in rows and columns. 13. The memory device of claim 12 wherein the outputted address comprises a specified row and a specified column of the selected one of the memory cells. 14. The memory device of claim 11, wherein the address signals are coupled to the configurable address buffer through a bus, and wherein the address configuration selector is operable to develop the control signal as a function of a width of the bus. 15. The memory device of claim 14 wherein the control signal is indicative of the first addressing configuration when the bus has a first width and the second addressing configuration when the bus has a second width. 16. The memory device of claim 11 wherein the first number of sets is one set. 17. The memory device of claim 16 wherein the second number of sets is two sets. 18. The memory device of claim 11, the configurable address buffer system operable to utilize a clock signal, and wherein the address signals in each of the sets in the second number are received at successive clock transitions. 19. The memory device of claim 11 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 20. The memory device of claim 11 wherein the address configuration selector comprises a mode register. 21. The memory device of claim 11 wherein the address configuration selector comprises fuses. 22. The memory device of claim 11 wherein the address configuration selector comprises anti-fuses. 23. The memory device of claim 11 wherein the address configuration selector comprises an externally applied mode select signal. 24. The memory device of claim 11 wherein the memory cells comprise dynamic random access memory cells. 25. The memory device of claim 11 wherein the memory device further comprises a plurality of arrays of memory cells. 26. A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; and a memory device coupled to the processor, the memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals; and one of a fuse and an anti-fuse operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 27. The computer system of claim 26 wherein the processor, input device, output device, and memory device are coupled through a processor bus. 28. The computer system of claim 26 wherein the addressable array of memory cells are arranged in rows and columns. 29. The computer system of claim 28 wherein the outputted address comprises a specified row and a specified column of the selected one of the memory cells. 30. The computer system of claim 26, wherein the address signals are coupled to the configurable address buffer through a bus, and wherein the address configuration selector is operable to develop the control signal as a function of a width of the bus. 31. The computer system of claim 30 wherein the control signal is indicative of the first addressing configuration when the bus has a first width and the second addressing configuration when the bus has a second width. 32. The computer system of claim 26 wherein the first number of sets is one set. 33. The computer system of claim 32 wherein the second number of sets is two sets. 34. The computer system of claim 26, the configurable address buffer system operable to utilize a clock signal, and wherein the address signals in each of the sets in the second number are each received during successive clock periods. 35. The computer system of claim 26, the configurable address buffer system operable to utilize a clock signal, and wherein the address signals in each of the sets in the second number are received at successive clock transitions. 36. The computer system of claim 26 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 37. The computer system of claim 26 wherein the address configuration selector comprises a mode register. 38. The computer system of claim 26 wherein the address configuration selector comprises an externally applied mode select signal. 39. The computer system of claim 26 wherein the memory cells comprise dynamic random access memory cells. 40. The computer system of claim 26 wherein the memory device further comprises a plurality of arrays of memory cells. 41. A method of customizing a configurable address buffer system for addressing a memory device comprising: coupling a control signal to the address buffer system to select a first or second addressing configuration; in the first addressing configuration, sequentially applying a first group of address signals to an address bus responsive to a first transition of a clock signal and a second group of address signals to the address bus responsive to a second transition of the clock signal; and in a second addressing configuration, simultaneously applying the first group of address signals and the second group of address signals to the address bus responsive to the first transition of the clock signal. 42. The method of claim 41 wherein the first and second transitions of the clock signal comprises a first rising edge and a first falling edge that is immediately adjacent to the first rising edge. 43. The method of claim 41 wherein the first and second transitions of the clock signal comprises a first rising edge and a second rising edge respectively. 44. The method of claim 41 wherein the first and second transitions of the clock signal comprises spacing a second transition of the clock signal by a predetermined factor of clock periods relative to a first transition of the clock signal. 45. The method of claim 41 wherein the control signal further comprises selecting the first or second addressing configuration based on selecting a bandwidth size. 46. The method of claim 41 further comprising: processing a first read operation from the first and second group of address signals to output an address; and processing a second read operation from a second and third group of address signals in either the first or second addressing configuration, the second read operation being processed concurrently with the first read operation. 47. The method of claim 46 wherein processing the first and second read operations further comprises processing a read operation having a burst length of two. 48. The method of claim 46 further comprising spacing the first and second group of address signals of the first read operation by a predetermined factor of clock periods relative to the third and fourth group of address signals of the second read operation. 49. The method of claim 41 wherein the act of sequentially applying the groups of address signals in the first configuration comprises applying N address signals through N bits of an address bus, and wherein the act of simultaneously applying the groups of address signals in the second configuration comprises applying M sets of N/M address signals through N/M bits of the address bus. 50. A method of addressing a memory device comprising: in a first addressing configuration, applying a first group of address signals to the memory device responsive to a first transition of a clock signal and applying a second group of address signals to the memory device responsive to a second transition of the clock signal; and in a second addressing configuration, simultaneously applying the first group of address signals and the second group of address signals to the memory device responsive to the first transition of the clock signal in a manner that causes the time period for addressing the groups of address signals in the second address configuration to be different relative to the time period for addressing the groups of address signals in the first address configuration. 51. The method of claim 50 wherein the time period for addressing the group of signals in the second configuration is less than the time period for addressing the group of signals in the first configuration. 52. The method of claim 50 wherein the first and second transitions of the clock signal comprises a first rising edge and a first falling edge that is immediately adjacent to the first rising edge. 53. The method of claim 50 wherein the first and second transitions of the clock signal comprises a first rising edge and a second rising edge respectively. 54. The method of claim 50 wherein the first and second transitions of the clock signal comprises spacing a second transition of the clock signal by a predetermined factor of clock periods relative to a first transition of the clock signal. 55. The method of claim 50 further comprising: processing a first read operation from the first and second group of address signals to output an address; and processing a second read operation from a second and third group of address signals in either the first or second addressing configuration, the second read operation being processed concurrently with the first read operation. 56. The method of claim 55 wherein processing the first and second read operations further comprises processing a read operation having a burst length of two. 57. The method of claim 55 further comprising spacing the first and second group of address signals of the first read operation by a predetermined factor of clock periods relative to the third and fourth group of address signals of the second read operation. 58. The method of claim 50 wherein the act of applying the groups of address signals in the first configuration comprises applying N address signals through N bits of an address bus, and wherein the act of simultaneously applying the groups of address signals in the second configuration comprises applying M sets of N/M address signals through N/M bits of the address bus. 59. A method of addressing a memory device comprising: in a first addressing configuration, applying a first group of address signals to an address bus responsive to a first transition of a clock signal and applying a second group of address signals to the address bus responsive to a second transition of the clock signal; and in a second addressing configuration, simultaneously applying the first group of address signals and the second group of address signals to the address bus responsive to the first transition of the clock signal in a manner such that a bandwidth size for the address bus utilized in the second addressing configuration is different from a bandwidth size for the address bus utilized in the first address configuration. 60. The method of claim 59 wherein the bandwidth size for addressing the group of signals to the address bus in the second configuration is less than the bandwidth size for addressing the group of signals to the address bus in the first configuration. 61. The method of claim 59 wherein the first and second transitions of the clock signal comprises a first rising edge and a first falling edge that is immediately adjacent to the first rising edge. 62. The method of claim 59 wherein the first and second transitions of the clock signal comprises a first rising edge and a second rising edge respectively. 63. The method of claim 59 wherein the first and second transitions of the clock signal comprises spacing a second transition of the clock signal by a predetermined factor of clock periods relative to a first transition of the clock signal. 64. The method of claim 59 further comprising: processing a first read operation from the first and second group of address signals to output an address; and processing a second read operation from a second and third group of address signals in either the first or second addressing configuration, the second read operation being processed concurrently with the first read operation. 65. The method of claim 64 wherein processing the first and second read operations further comprises processing a read operation having a burst length of two. 66. The method of claim 64 further comprising spacing the first and second group of address signals of the first read operation by a predetermined factor of clock periods relative to the third and fourth group of address signals of the second read operation. 67. The method of claim 59 wherein the act of applying the groups of address signals in the first configuration comprises applying N address signals through N bits of an address bus, and wherein the act of simultaneously applying the groups of address signals in the second configuration comprises applying M sets of N/M address signals through N/M bits of the address bus. 68. A configurable address buffer system operable to utilize a clock signal and to receive at least one set of address signals and output an address, the system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals, the address signals in each of the sets in the second number being received during successive clock periods; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 69. The system of claim 68 wherein the address signals are coupled to the configurable address buffer through a bus, and wherein the address configuration selector is operable to develop the control signal as a function of a width of the bus. 70. The system of claim 68 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 71. A configurable address buffer system operable to receive at least one set of address signals and output an address, the system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals, the configurable address buffer comprising: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 72. A configurable address buffer system operable to receive at least one set of address signals and output an address, the system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals; and a mode register operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 73. A configurable address buffer system operable to receive at least one set of address signals and output an address, the system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals; and one of a fuse and an anti-fuse operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 74. A memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer, the configurable address buffer operable in a first addressing configuration to output the address utilizing one set of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing two sets of the address signals; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 75. A memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals, the configurable address buffer comprising: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 76. A memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals; and a mode register operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 77. The memory device of claim 76 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 78. A memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals; and one of a fuse and an anti-fuse operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 79. The memory device of claim 78 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 80. A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; and a memory device coupled to the processor, the memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing one set of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing two sets of the address signals; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 81. The computer system of claim 80 wherein the address configuration selector comprises an externally applied mode select signal. 82. The computer system of claim 80 wherein the memory cells comprise dynamic random access memory cells. 83. A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; and a memory device coupled to the processor, the memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to utilize a clock signal and to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals, the address signals in each of the sets in the second number being received during successive clock periods; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 84. The computer system of claim 83 wherein the configurable address buffer further comprises: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders. 85. The computer system of claim 83 wherein the address configuration selector comprises an externally applied mode select signal. 86. A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; and a memory device coupled to the processor, the memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals, the configurable address buffer comprising: a first decoder operable to receive address signals and output at least a portion of a row or column address; a second decoder operable to receive address signals and output at least a portion of a row or column address; and an input buffer coupled to the first and second decoders, the input buffer operable in the first addressing configuration to receive at least a portion of the address signals in each of the first number of sets and to sequentially couple each of the received portions of the address signals in the first number of sets to the first decoder, the first input buffer operable in the second addressing configuration to receive at least a portion of the address signals in each of the second number of sets and alternately couple the received portions of the address signals in the second number of sets to the first and second decoders; and an address configuration selector operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 87. A computer system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; and a memory device coupled to the processor, the memory device comprising: an addressable array of memory cells; and a configurable address buffer system coupled to the addressable array of memory cells, the configurable address buffer system operable to receive at least one set of address signals and output an address of a selected one of the memory cells, the configurable address buffer system comprising: a configurable address buffer receiving the address signals, the configurable address buffer operable in a first addressing configuration to output the address utilizing a first number of sets of the address signals, the configurable address buffer further operable in a second addressing configuration to output the address utilizing a second number of sets of the address signals; and a mode register operable to couple a control signal to the configurable address buffer, the control signal causing the configurable address buffer to operate according to the first or the second addressing configuration. 88. The computer system of claim 87 wherein the memory cells comprise dynamic random access memory cells.