Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-007/38
H03K-019/173
출원번호
US-0082203
(2005-03-15)
등록번호
US-7330050
(2008-02-12)
발명자
/ 주소
Redgrave,Jason
출원인 / 주소
Tabula, Inc.
대리인 / 주소
Adeli & Tollen LLP
인용정보
피인용 횟수 :
37인용 특허 :
104
초록▼
Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry
Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.
대표청구항▼
I claim: 1. A configurable integrated circuit (IC) comprising: a) a plurality of configurable circuits; b) a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) an output circuit for outputting da
I claim: 1. A configurable integrated circuit (IC) comprising: a) a plurality of configurable circuits; b) a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) an output circuit for outputting data stored in the storage elements; c) said output circuit comprising a first set of interconnects for receiving at least a first repeating periodic signal and a set of sense amplifiers for sensing the data stored in the storage elements, said first set of interconnects further for periodically outputting data from at least two storage elements to the configurable circuits. 2. The configurable IC of claim 1 further comprising a second set of interconnects connected to the output circuit, said second set of interconnects for receiving at least a second repeating periodic signal. 3. The configurable IC of claim 2, wherein the first and second periodic signals have different frequencies. 4. The configurable IC of claim 2, wherein the first periodic signal has a first frequency and the second periodic signal has a second frequency, said first and second sets of interconnects for providing stored data from the storage elements to the configurable circuits at a third frequency. 5. The configurable IC of claim 2, wherein the second set of interconnects directly connects to the output circuit. 6. The configurable IC of claim 1, wherein each sense amplifier is a level converting sense amplifier. 7. The configurable IC of claim 6, wherein each sense amplifier is level converting because the storage elements store data at a reduced voltage level. 8. The configurable IC of claim 1, wherein at least one sense amplifier is for controllably sensing the data stored in a plurality of storage elements. 9. The configurable IC of claim 8, wherein each sense amplifier controllably connects to a storage element through the interconnects in the first set of interconnects. 10. The configurable IC of claim 8, wherein the set of sense amplifiers comprises a plurality of sense amplifiers. 11. The configurable IC of claim 1, wherein the data is configuration data for configuring the configurable circuits. 12. An electronic device comprising: a configurable integrated circuit (IC) comprising: a plurality of configurable circuits; a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) an output circuit for outputting data stored in the storage elements; said output circuit comprising a first set of interconnects for receiving at least a first repeating periodic signal and a set of sense amplifiers for sensing the data stored in the storage elements, said first set of interconnects further for periodically outputting data from at least two storage elements to the configurable circuits. 13. The electronic device of claim 12, wherein the configurable IC further comprises a second set of interconnects connected to the output circuit, said second set of interconnects for receiving at least a second repeating periodic signal. 14. The electronic device of claim 13, wherein the first and second periodic signals have different first and second frequencies. 15. The electronic device of claim 14, said first and second sets of interconnects for providing stored data from the storage elements to the configurable circuits at a third frequency. 16. The electronic device of claim 13, wherein the second set of interconnects directly connects to the output circuit. 17. The electronic device of claim 12, wherein at least one sense amplifier is for controllably sensing the data stored in a plurality of storage elements. 18. The electronic device of claim 17, wherein each sense amplifier controllably connects to a storage element through the interconnects in the first set of interconnects. 19. A configurable integrated circuit (IC) comprising: a) a plurality of configurable circuits; b) a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) a sense amplifier for outputting data stored in the storage elements; c) said sense amplifier comprising first set of a interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits. 20. The configurable IC of claim 19, wherein the data is configuration data for configuring the configurable circuits. 21. The configurable IC of claim 20, wherein the configurable IC is a reconfigurable IC, wherein a configurable circuit receives at least two different configuration data sets at a particular frequency related to the frequency of the first periodic signal. 22. A configurable integrated circuit (IC) comprising: a) a plurality of configurable circuits; b) a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) an output circuit for outputting data stored in the storage elements; c) said output circuit comprising a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits; d) a second set of interconnects connected to the output circuit, said second set of interconnects for receiving at least a second repeating periodic signal; e) a set of intervening circuits between the second set of interconnects and the output circuit. 23. The configurable IC of claim 22, wherein the first and second periodic signals have different first and second frequencies. 24. The configurable IC of claim 23, said first and second sets of interconnects for providing stored data from the storage elements to the configurable circuits at a third frequency. 25. The configurable IC of claim 22, wherein the intervening circuits include a set of sense amplifiers for sensing the data stored in the storage elements. 26. An electronic device comprising: a configurable integrated circuit (IC) comprising: a plurality of configurable circuits; a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) an output circuit for outputting data stored in the storage elements; said output circuit comprising a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits; a second set of interconnects connected to the output circuit, said second set of interconnects for receiving at least a second repeating periodic signal; a set of intervening circuits between the second set of interconnects and the output circuit. 27. The electronic device of claim 26, wherein the first and second periodic signals have different first and second frequencies, said first and second sets of interconnects for providing stored data from the storage elements to the configurable circuits at a third frequency. 28. An electronic device comprising: a configurable integrated circuit (IC) comprising: a plurality of configurable circuits; a plurality of storage circuits, each storage circuit comprising (i) a plurality of storage elements for storing data for the configurable circuits and (ii) a sense amplifier for outputting data stored in the storage elements; said sense amplifier comprising a first set of interconnects for receiving at least a repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.
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Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M., Efficient interconnect network for use in FPGA device having variable grain architecture.
Agrawal, Om P.; Fontana, Fabiano; Bosco, Gilles M., Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use.
Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
Ghia, Atul V.; Vadi, Vasisht M.; Bekele, Adebabay M.; Costello, Philip D.; Verma, Hare K., Low jitter clock for a physical media access sublayer on a field programmable gate array.
Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
Poplingher Mircea ; Chen Wenliang ; Suryanarayanan Ganesh ; Chen Wayne W. ; Lo Roger Y., Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
Motomura Masato,JPX, Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Blodget, Brandon J.; McMillan, Scott P.; James-Roxby, Philip B.; Sundararajan, Prasanna; Keller, Eric R.; Curd, Derek R.; Kalra, Punit S.; LeBlanc, Richard J.; Eck, Vincent P., Reconfiguration of a programmable logic device using internal control.
Om P. Agrawal ; Claudia A. Stanley ; Xiaojie (Warren) He ; Larry R. Metzger ; Robert A. Simon ; Kerry A. Ilgenstein, Scalable architecture for high density CPLD's having two-level hierarchy of routing resources.
Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits.
Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
Balasubramanian,Rabindranath; Zhu,Limin; Speers,Theodore; Bakker,Gregory, System-on-a-chip integrated circuit including dual-function analog and digital inputs.
Takehara, Jun; Aramaki, Naruhiko; Kawamura, Toshikazu; Sameda, Yoshito; Nakatani, Hiroshi; Okabe, Motohiko; Yoshida, Yukitaka, Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line.
Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.
Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
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