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Configuration in a configurable system on a chip 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-003/00
출원번호 US-0016427 (2004-12-16)
등록번호 US-7330912 (2008-02-12)
발명자 / 주소
  • Fox,Brian
  • Papaliolios,Andreas
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman, LLC
인용정보 피인용 횟수 : 71  인용 특허 : 36

초록

The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources

대표청구항

The invention claimed is: 1. A method of initializing a configurable system on a chip (CSoC), the CSoC including configurable system logic (CSL), the method comprising: checking for one of a serial and a parallel output device external to the CSoC and coupled to a memory interface unit (MIU) in the

이 특허에 인용된 특허 (36)

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  8. Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
  9. Shaila Hanrahan ; Christopher E. Phillips, Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit.
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  31. Normoyle Kevin B. ; Ebrahim Zahir ; Nishtala Satyanarayana ; Van Loo William C. ; Coffin ; III Louis F., Pipelined distributed bus arbitration system.
  32. Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor) Duong Khue (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA) Erickson Charles R. (Fremont CA) Carter William S. (Santa Clara C, Programmable connector for programmable logic device.
  33. Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
  34. Upton Eric L., Reconfigurable processor for executing successive function sequences in a processor operation.
  35. Pierce Kerry M. (Fremont CA) Erickson Charles R. (Fremont CA), Soft wakeup output buffer.
  36. Topolewski Todd J. (Oakland CA) Weir Christine M. (Santa Cruz CA) Reynolds Bart (Campbell CA) Smuts Julia M. (San Jose CA) Wynn Pardner (San Jose CA) Trimberger Stephen M. (San Jose CA), Structure and method for manually controlling automatic configuration in an integrated circuit logic block array.

이 특허를 인용한 특허 (71)

  1. Redgrave, Jason; Hutchings, Brad; Teig, Steven; Schmit, Herman; Khubchandani, Teju, Accessing multiple user states concurrently in a configurable IC.
  2. Fallon, James J.; McErlain, Stephen J., Asymmetric data decompression systems.
  3. Fallon, James J.; McErlain, Stephen J., Asymmetric data decompression systems.
  4. Fallon, James J.; McErlain, Stephen J., Bandwidth sensitive data compression and decompression.
  5. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
  6. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
  7. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.
  8. Redgrave, Jason; Khubchandani, Teju; Schmit, Herman, Configuration network for an IC.
  9. Fallon, James J., Data compression systems and method.
  10. Fallon, James J., Data compression systems and methods.
  11. Fallon, James J., Data compression systems and methods.
  12. Fallon, James J., Data compression systems and methods.
  13. Fallon, James J., Data compression systems and methods.
  14. Fallon, James J., Data compression systems and methods.
  15. Fallon, James J., Data compression systems and methods.
  16. Fallon, James J., Data compression systems and methods.
  17. Fallon, James J., Data compression systems and methods.
  18. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, II, Carlton J., Data feed acceleration.
  19. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, II, Carlton J., Data feed acceleration.
  20. Hutchings, Brad; Teig, Steven, Dynamically tracking data values in a configurable IC.
  21. Hutchings, Brad, IC with deskewing circuits.
  22. Hutchings, Brad, IC with deskewing circuits.
  23. Miller, Marc; Teig, Steven; Hutchings, Brad, Integrated circuit (IC) with primary and secondary networks and device containing such an IC.
  24. Miller, Marc; Teig, Steven; Hutchings, Brad; Thom, Danny, Integrated circuit (IC) with primary and secondary networks and device containing such an IC.
  25. Hutchings, Brad; Redgrave, Jason, Integrated circuit with delay selecting input selection circuitry.
  26. Xiao, Ping, Methods and apparatus for configuring and reconfiguring a partial reconfiguration region.
  27. Xiao, Ping, Methods and apparatus for configuring and reconfiguring a partial reconfiguration region.
  28. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, Carlton J., Methods for encoding and decoding data.
  29. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, II, Carlton J., Methods for encoding and decoding data.
  30. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, II, Carlton J., Methods for encoding and decoding data.
  31. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, II, Carlton J., Methods for encoding and decoding data.
  32. Fox, Brian, Micro-granular delay testing of configurable ICs.
  33. Olgiati, Andrea; Baker, Matthew Pond; Teig, Steven, Non-intrusive monitoring and control of integrated circuits.
  34. Olgiati, Andrea; Baker, Matthew Pond; Teig, Steven, Non-intrusive monitoring and control of integrated circuits.
  35. Olgiati, Andrea; Baker, Matthew Pond; Teig, Steven, Non-intrusive monitoring and control of integrated circuits.
  36. Hutchings, Brad; Redgrave, Jason; Khubchandani, Teju; Schmit, Herman; Teig, Steven, Runtime loading of configuration data in a configurable IC.
  37. Hutchings, Brad; Redgrave, Jason; Khubchandani, Teju; Schmit, Herman; Teig, Steven, Runtime loading of configuration data in a configurable IC.
  38. Hutchings, Brad; Redgrave, Jason; Khubehandani, Teju; Schmit, Herman; Teig, Steven, Runtime loading of configuration data in a configurable IC.
  39. Mardiks, Eitan; Bryant-Rich, Donald Ray, Storage device for mounting to a host.
  40. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  41. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  42. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, II, Carlton J., System and method for data compression.
  43. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J., System and method for data feed acceleration and encryption.
  44. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J.; Melone, Carlton W., System and method for data feed acceleration and encryption.
  45. Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., System and method for electrical boot-device-reset signals.
  46. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power.
  47. Fallon, James J, System and methods for accelerated data storage and retrieval.
  48. Fallon, James J, System and methods for accelerated data storage and retrieval.
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  50. Fallon, James J., System and methods for accelerated data storage and retrieval.
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  52. Fallon, James J., System and methods for accelerated data storage and retrieval.
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  54. Fallon, James J.; McErlain, Stephen J., System and methods for video and audio data distribution.
  55. Fallon, James J.; McErlain, Stephen J., System and methods for video and audio data distribution.
  56. Fallon, James J.; McErlain, Stephen J., System and methods for video and audio data distribution.
  57. Fallon, James J.; McErlain, Stephen J., System and methods for video and audio data distribution.
  58. Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for accelerated loading of operating systems and application programs.
  59. Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for accelerated loading of operating systems and application programs.
  60. Fallon, James J.; Buck, John; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for accelerated loading of operating systems and application programs.
  61. Fallon, James J.; Pickel, Paul F.; McErlain, Stephen J., Systems and methods for data block decompression.
  62. Fallon, James J.; McErlain, Stephen J., Systems and methods for video and audio data storage and distribution.
  63. Fallon, James J.; McErlain, Stephen J., Systems and methods for video and audio data storage and distribution.
  64. Hutchings, Brad; Caldwell, Andrew; Teig, Steven, Translating a user design in a configurable IC for debugging the user design.
  65. Hutchings, Brad; Caldwell, Andrew; Teig, Steven, Translating a user design in a configurable IC for debugging the user design.
  66. Hutchings, Brad; Caldwell, Andrew; Teig, Steven, Transport network.
  67. Hutchings, Brad L.; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
  68. Hutchings, Brad; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
  69. Hutchings, Brad; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
  70. Hutchings, Brad; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
  71. Fallon, James J.; McErlain, Stephen J., Video data compression systems.
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