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Method of encapsulating packaged microelectronic devices with a barrier

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/48
  • H01L-021/02
  • H01L-023/48
  • H05K-003/30
출원번호 US-0516455 (2006-09-05)
등록번호 US-7332376 (2008-02-19)
발명자 / 주소
  • Cobbley,Chad A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Perkins Coie LLP
인용정보 피인용 횟수 : 0  인용 특허 : 157

초록

Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing

대표청구항

The invention claimed is: 1. A method of partially encapsulating a microelectronic device, comprising: coupling a die to a substrate, wherein the substrate comprises an encapsulation area; disposing a seal on a first side of the substrate, wherein at least a portion of the seal is positioned adjace

이 특허에 인용된 특허 (157)

  1. King Jerrold L. ; Brooks J. Mike ; Moden Walter L., Adhesion enhanced semiconductor die for mold compound packaging.
  2. Mess Leonard E. ; Corisis David J. ; Moden Walter L. ; Kinsman Larry D., Apparatus and methods of packaging and testing die.
  3. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Apparatus for circuit encapsulation.
  4. Weber Patrick O. (San Jose CA), Apparatus for encapsulating electronic packages.
  5. Thummel Steven G., Apparatus for encasing array packages.
  6. Akram Salman, Apparatus for packaging flip chip bare die on printed circuit boards.
  7. Johnson Mark S. ; Bolken Todd O., Asymmetric transfer molding method and an asymmetric encapsulation made therefrom.
  8. Moden Walter, BGA package and method of fabrication.
  9. Castro Abram M., Ball grid substrate for lead-on-chip semiconductor package.
  10. Castro, Abram M., Ball grid substrate for lead-on-chip semiconductor package.
  11. Corisis David ; Moden Walter, Chip package.
  12. Corisis David J., Chip scale package with heat spreader and method of manufacture.
  13. Hembree David R. ; Akram Salman, Circuit and method for heating an adhesive to package or rework a semiconductor die.
  14. John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
  15. Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Circuit encapsulation process.
  16. Tandy Patrick W. ; Brand Joseph M. ; Rumsey Brad D. ; Stephenson Steven R. ; Corisis David J. ; Bolken Todd O. ; Schrock Edward A. ; Dickey Brenton L., Controlling packaging encapsulant leakage.
  17. Ahmad Syed Sajid, Die positioning in integrated circuit packaging.
  18. Wood Alan G. ; Farnworth Warren M. ; Grigg Ford ; Akram Salman, Direct die contact (DDC) semiconductor package.
  19. Wood Alan G. ; Farnworth Warren M. ; Grigg Ford ; Akram Salman, Direct die contact (DDC) semiconductor package.
  20. SinghDeo Narendra N. (New Haven CT) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL), Electronic packaging of components incorporating a ceramic-glass-metal composite.
  21. Wensel Richard W., Encapsulated integrated circuit packaging.
  22. Poinelli Renato,ITX ; Corno Marziano,ITX, Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic devi.
  23. Nambu Seigo (Tokyo JPX) Takei Shinji (Tokyo JPX) Okuaki Hiroshi (Tokyo JPX), Heat-resistant plastic semiconductor device.
  24. Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.
  25. Chang Chi S. (Endicott) Hoffarth Joseph G. (Binghamton) Markovich Voya R. (Endwell) Snyder Keith A. (Vestal) Wiley John P. (Vestal NY), High density circuit board and method of making same.
  26. Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Brooks Mike ; Cloud Eugene, High density semiconductor package.
  27. Combs Edward G. (Foster City CA), High power dissipation plastic encapsulated package for integrated circuit die.
  28. Corisis David J. ; Keeth Brent, High speed IC package configuration.
  29. Fox ; III Angus C. (Boise ID) Farnworth Warren M. (Nampa ID), High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vi.
  30. Mazumder Mohiuddin M., Hole geometry of a semiconductor package substrate.
  31. Corisis David J., IC package with dual heat spreaders.
  32. Corisis David J. ; Reynolds Tracy ; Slaughter Michael ; Cram Daniel ; Nevill Leland R. ; King Jerrold L., Integrated circuit package alignment feature.
  33. Akram Salman ; Farnworth Warren M., Integrated circuit package and method of fabrication.
  34. Matsumoto Kazuhiro (Tokyo JPX), Integrated circuit package having stress reducing recesses.
  35. Corisis David J. ; Reynolds Tracy ; Slaughter Michael ; Cram Daniel ; Nevill Leland R. ; King Jerrold L., Integrated circuit package including lead frame with electrically isolated alignment feature.
  36. Manzione Louis T. (Summit) Patel C. Kumar (Summit NJ), Integrated circuit package with strain relief grooves.
  37. Syed Sajid Ahmad, Interconnecting substrates for electrical coupling of microelectronic components.
  38. Corisis David J. ; Brooks Jerry M. ; Lee Terry R., Lead frame assemblies with voltage reference plane and IC packages including same.
  39. Japp Robert M. ; Poliks Mark D., Low CTE power and ground planes.
  40. Kinsman Larry D., Low profile ball grid array package.
  41. Moden Walter L. ; King Jerrold L. ; Brooks Jerry M., Low profile multi-IC chip package connector.
  42. Shintai Akira,JPX, Manufacturing method for a resin sealed semiconductor device.
  43. Farnworth Warren ; Kinsman Larry ; Moden Walter, Method and apparatus for a semiconductor package for vertical surface mounting.
  44. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  45. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  46. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  47. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  48. Akram Salman, Method and apparatus for packaging flip chip bare die on printed circuit boards.
  49. Phillips Eugene (Diamond Bar CA), Method for conditioning drilled holes in multilayer wiring boards.
  50. Variot Patrick (San Jose CA), Method for encapsulating an integrated circuit package.
  51. Ishii Masaaki,JPX, Method for encapsulation of semiconductor devices with resin and leadframe therefor.
  52. Thummel Steven G., Method for encasing array packages.
  53. Jiang Tongbi ; Schrock Edward, Method for fabricating BGA package using substrate with patterned solder mask open in die attach area.
  54. Bolken Todd O. ; Peters David L. ; Tandy Patrick W. ; Cobbley Chad A., Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities.
  55. McShane Michael B. (Austin TX) Casto James J. (Austin TX) Joiner Bennett A. (Austin TX), Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suc.
  56. Djennas Frank (Austin TX) Nomi Victor K. (Round Rock TX) Pastore John R. (Leander TX) Reeves Twila J. (Austin TX) Postlethwait Les (Lexington TX), Method for making semiconductor device having no die supporting surface.
  57. Odashima Teikou,JPX ; Matsui Mikio,JPX ; Sugizaki Yoshiaki,JPX ; Nakazawa Takahito,JPX, Method for manufacturing semiconductor device and apparatus for resin-encapsulating.
  58. Drummond Brian (Austin TX), Method for molding using venting pin.
  59. Kinsman Larry D. (Boise ID), Method for packaging a semiconductor die.
  60. Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID) Doan Trung T. (Boise ID) Jacobson John O. (Boise ID), Method for packaging semiconductor dice.
  61. Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Method for testing semiconductor dice with conventionally sized temporary packages.
  62. Ahmad, Syed Sajid, Method of Interconnecting substrates for electrical coupling of microelectronic components.
  63. Cobbley,Chad A., Method of encapsulating interconnecting units in packaged microelectronic devices.
  64. Manzione Louis T. (Summit NJ) Weld John D. (Succasunna NJ), Method of encapsulating large substrate devices using reservoir cavities for balanced mold filling.
  65. Taniguchi Fumihiko,JPX ; Honna Koji,JPX ; Kumagaya Yoshikazu,JPX, Method of fabricating semiconductor having through hole.
  66. Farnworth Warren M., Method of forming overmolded chip scale package and resulting product.
  67. Brooks Jerry M. ; Thummel Steven G., Method of making a cavity ball grid array apparatus.
  68. Schachter Herbert I. (86 Campbell St. New Hyde Park ; Long Island NY 11040), Method of making a multi-level circuit board.
  69. King Jerold L. ; Brooks Jerry M., Method of making a multichip semiconductor package.
  70. Rose Ren (Voisin-Le-Bretonneux FRX), Method of making an electronic module for a memory card and an electronic module thus obtained.
  71. Knapp James H. ; Scribner Cliff J. ; Laninga ; Sr. Albert J., Method of manufacturing a semiconductor component.
  72. Crowley Sean T. ; Cheney Gerald L. ; Razu David S., Method of molding plastic semiconductor packages.
  73. Chun Hung Lin TW, Method of molding semiconductor device and molding die for use therein.
  74. Miyajima Fumio,JPX, Method of operating a molding machine with release film.
  75. Sakai Kunito (Hyogo JPX) Matsuda Sadamu (Hyogo JPX) Takahama Takashi (Hyogo JPX), Method of resin encapsulating a semiconductor device.
  76. Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.
  77. Tripard Jason E., Methods of forming integrated circuit packages.
  78. Bolken, Todd O., Microelectronic devices and microelectronic die packages.
  79. Akram Salman ; Hembree David R. ; Farnworth Warren M., Micromachined chip scale package.
  80. Akram Salman ; Hembree David R. ; Farnworth Warren M., Micromachined chip scale package.
  81. Chia Chok J. (Campbell CA) Lim Seng-Sooi (San Jose CA), Modified lead frame for reducing wire wash in transfer molding of IC packages.
  82. Farnworth Warren M. ; Corisis David J. ; Akram Salman, Modular die sockets with flexible interconnects for packaging bare semiconductor die.
  83. Miles Barry M. ; Mullen ; III William B. ; Gold Glenn E., Moisture enhanced ball grid array package.
  84. Freyman Bruce J. (Plantation FL) Juskey Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL), Moisture relief for chip carrier.
  85. Miles Barry M., Moisture relief for chip carriers.
  86. Lee Sang S. ; Loh William M., Mold flow regulating dam ring.
  87. Chia Chok J. ; Lim Seng-Sooi ; Low Qwai H., Molded array integrated circuit package.
  88. Weld John David, Molded encapsulated electronic component.
  89. Izumi Atsuhiko (Tokyo JPX) Inaba Takehito (Tokyo JPX) Azuma Kousuke (Tokyo JPX), Molding die for sealing semiconductor device with reduced resin burrs.
  90. Kao-Yu Hsu TW; Chun Hung Lin TW; Tao-Yu Chen TW, Molding method for BGA semiconductor chip package.
  91. Jain Praveen (Gilbert AZ) Kar Rudra (Mesa AZ), Molding technique for molding plastic packages.
  92. Ferri Stefano,ITX ; Rossi Roberto,ITX, Package for electronic device having a fully insulated dissipator.
  93. Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
  94. Akram Salman ; Wark James M., Packaged die on PCB with heat sink encapsulant.
  95. Cobbley, Chad A., Packaged microelectronic devices with interconnecting units.
  96. James, Stephen L.; Cobbley, Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  97. James,Stephen L.; Cobbley,Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  98. Bolken Todd O. ; Baerlocher Cary J. ; Corisis David J. ; Cobbley Chad A., Packages for semiconductor die.
  99. Hodges Joe W., Packaging for bare dice employing EMR-sensitive adhesives.
  100. Wood Alan G. (Boise ID) Corbett Tim J. (Boise ID), Packaging for semiconductor logic devices.
  101. Wood Alan G. ; Corbett Tim J., Packaging for semiconductor logic devices.
  102. Kinsman Larry (Boise ID), Packaging means for a semiconductor die having particular shelf structure.
  103. Jiang Tongbi ; Yin Zhiping, Passivation layer for packaged integrated circuits.
  104. Nambu Seigo (Tokyo JPX) Fukazawa Hiroyuki (Tokyo JPX) Takei Shinji (Tokyo JPX), Plastic-sealed IC device of heat-resistant construction.
  105. Wang Kuo K. ; Han Sejin, Pressurized underfill encapsulation of integrated circuits.
  106. Ha Sun Ho,KRX ; Heo Young Wook,KRX, Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package.
  107. Chobot Ivan I. (Whitby NY CAX) Covert John A. (Binghamton NY) Haight Randy L. (Waverly NY) Mansfield Keith D. (New Milford PA) Miller Donald W. (Newark Valley NY) Neira Reinaldo A. (Endicott NY) Petr, Printed circuit board or card thermal mass design.
  108. Steffen Francis,FRX, Process for manufacturing a chip card micromodule with protection barriers.
  109. Wood Alan G. ; Akram Salman ; Farnworth Warren M., Process for manufacturing a semiconductor package with bi-substrate die.
  110. Wood Alan G. ; Farnworth Warren M., Process for packaging a semiconductor die using dicing and testing.
  111. Cobbley Chad, Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member.
  112. Beddingfield Stanley C. ; Higgins ; III Leo M. ; Gentile John C., Process for underfilling a flip-chip semiconductor device.
  113. Farnworth Warren M. ; Wood Alan G., Process of making a glass semiconductor package.
  114. Wojnarowski Robert J. (Ballston Lake NY) Cole Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Daum Wolfgang (Schenectady NY), Processing low dielectric constant materials for high speed electronics.
  115. McMillan ; II Richard Keith ; Jairazbhoy Vivek Amir ; Gordon Robert Joseph ; Garfinkel George Albert, Reflow soldering to mounting pads with vent channels to avoid skewing.
  116. Azuma Kousuke,JPX, Resin sealing mold die set with less resin remainder for semiconductor device.
  117. Tsuji Yukihiro (Kumamoto JPX), Resin-sealed semiconductor device.
  118. Sawaya Hiromichi (Kawasaki JPX) Ishigami Toshio (Kawasaki JPX), Resin-sealed type semiconductor device and method for manufacturing the same.
  119. Kanesaka Kenji,JPX, Sealed semiconductor device with positional deviation between upper and lower molds.
  120. Wilson Howard P. (Austin TX) Martin Fonzell D. J. (Austin TX), Self-opening vent hole in an overmolded semiconductor device.
  121. King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID), Semiconductor chip package.
  122. King Jerrold L. ; Nevill Leland R., Semiconductor chip package.
  123. Lee Kyu Jin,KRX ; Choi Wan Gyun,KRX, Semiconductor chip package using flexible circuit board with central opening.
  124. Tsuruzono Kimihiro,JPX, Semiconductor device.
  125. Yamaji Yasuhiro (Kawasaki JPX) Takahashi Kenji (Yokohama JPX) Hirata Seiichi (Yokosuka JPX) Sakurai Toshiharu (Yokohama JPX), Semiconductor device.
  126. Yamazaki Shunpei (Tokyo JPX), Semiconductor device having a film-covered packaged component.
  127. Romano\ Luigi (Monza ITX), Semiconductor device mounted in a highly flexible, segmented package, provided with heat sink.
  128. Akram Salman, Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices.
  129. Larson Charles ; Fernandez John, Semiconductor lead frame and package with stiffened mounting paddle.
  130. Corisis David J., Semiconductor package.
  131. Sasaki Takaaki,JPX, Semiconductor package.
  132. Corisis David J., Semiconductor package having downset leadframe for reducing package bow.
  133. Corisis David J., Semiconductor package having downset leadframe for reducing package bow.
  134. Akram Salman, Semiconductor package having interlocking heat sinks and method of fabrication.
  135. Kinsman Larry D., Semiconductor package having metal foil die mounting plate.
  136. Moden Walter, Semiconductor package having stacked dice and leadframes and method of fabrication.
  137. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Semiconductor package including flex circuit, interconnects and dense array external contacts.
  138. Brooks Mike ; Moden Walter L., Semiconductor package with heat sink and method of fabrication.
  139. Brooks Mike ; Moden Walter L., Semiconductor package with heat sink and method of fabrication.
  140. Takamichi Hiroshi,JPX ; Nakada Yoshikazu,JPX, Semiconductor package with improved moisture vapor relief function and method of fabricating the same.
  141. Farnworth Warren M. ; Hembree David R. ; Gochnour Derek ; Akram Salman ; Jacobson John O. ; Wark James M. ; Thummel Steven G., Semiconductor package with pre-fabricated cover and method of fabrication.
  142. Hembree David R. ; Akram Salman ; Gochnour Derek ; Farnworth Warren M., Semiconductor package with wire bond protective member.
  143. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Single piece package for semiconductor die.
  144. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.
  145. Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Temporary package for semiconductor dice.
  146. Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Temporary package for semiconductor dice.
  147. Hembree David R. ; Farnworth Warren M ; Wood Alan G. ; Akram Salman, Temporary semiconductor package having dense array external contacts.
  148. Chamberlin Bruce J. ; Ferrill Mitchell G. ; Stutzman Randall J. ; Thiel George H., Thermal/electrical break for printed circuit boards.
  149. Kierse Oliver J.,IEX, Thermally efficient integrated circuit package.
  150. Jiang Tongbi ; Johnson Mark S., Thermally enhanced semiconductor package.
  151. Corisis David J., Transverse hybrid LOC package.
  152. Burns Carmen D., Ultra high density integrated circuit packages.
  153. Mitchell Craig S. ; Distefano Thomas H., Vacuum dispense apparatus for dispensing an encapsulant.
  154. Kinsman Larry D. ; Brooks Jerry M., Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages.
  155. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
  156. Akram Salman ; Wood Alan G., Wafer-level package and methods of fabricating.
  157. Lee Kyu Jin,KRX ; Jeong Do Soo,KRX ; Kim Jae June,KRX, Wire bond packages for semiconductor chips and related methods and assemblies.
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