Reduced complexity coding system using iterative decoding
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-027/22
H04L-027/06
H04L-027/20
출원번호
US-0131611
(2002-04-23)
등록번호
US-7333571
(2008-02-19)
발명자
/ 주소
Simon,Marvin K.
Divsalar,Dariush
출원인 / 주소
California Institute of Technology
인용정보
피인용 횟수 :
5인용 특허 :
11
초록
A concatenated coding scheme, using an outer coder, interleaver, and the inner coder inherent in an FQPSK signal to form a coded FQPSK signal. The inner coder is modified to enable interactive decoding of the outer code.
대표청구항▼
What is claimed is: 1. A method of encoding, comprising: performing a first outer encoding on a first portion of an input sequence of bits to produce first outer encoded bits; performing a second outer encoding on a second portion of the input sequence of bits to produce second outer encoded bits;
What is claimed is: 1. A method of encoding, comprising: performing a first outer encoding on a first portion of an input sequence of bits to produce first outer encoded bits; performing a second outer encoding on a second portion of the input sequence of bits to produce second outer encoded bits; bit interleaving said first outer encoded bits to produce first interleaved encoded bits; bit interleaving said second outer encoded bits to produce second interleaved encoded bits; performing a modified FQPSK modulation on said first interleaved encoded bits and said second interleaved encoded bits to produce I and Q waveform sequences, wherein said performing the modified FQPSK modulation realizes a modulation with memory, wherein said performing the modified FQPSK modulation includes: performing an I-channel recursive encoding on the first interleaved encoded bits to generate I encoder outputs; performing a Q-channel recursive encoding on the second interleaved encoded bits to generate Q encoder outputs; performing a signal mapping on the I encoder outputs and the Q encoder outputs to generate said I and Q waveform sequences; wherein said I and Q waveform sequences are continuous in time. 2. The method of claim 1, wherein said performing the signal mapping generates the I waveform sequence based on the I encoder outputs and generates the Q waveform sequence based on the Q encoder outputs. 3. The method of claim 1, wherein said first and second outer encodings are linear encodings each with rate less than one. 4. The method of claim 1, wherein said first and second outer encodings are each repetition encodings. 5. The method of claim 1, wherein said performing the modified FQPSK modulation also includes: performing quadrature modulation on quadrature carrier signals using respectively the I and Q waveform sequences to generate an output signal. 6. The method of claim 1 further comprising transmitting an output signal onto a channel, wherein the output signal is determined using the I and Q waveform sequences. 7. A method of encoding, comprising: outer encoding an input sequence of bits to produce outer encoded bits; bit interleaving said outer encoded bits to produce interleaved encoded bits; and performing a modified FQPSK modulation on said interleaved encoded bits to produce I and Q waveform sequences, wherein said performing the modified FQPSK modulation realizes a modulation with memory, wherein said performing the modified FQPSK modulation includes: performing an I-channel recursive encoding on a first portion of said interleaved encoded bits to generate I encoder outputs; performing a Q-channel recursive encoding on a second portion of said interleaved encoded bits to generate Q encoder outputs; performing a signal mapping on the I encoder outputs and the Q encoder outputs to generate said I and Q waveform sequences; wherein said I and Q waveform sequences are continuous in time. 8. The method of claim 7, wherein said performing the signal mapping generates the I waveform sequence based on the I encoder outputs and generates the Q waveform sequence based on the Q encoder outputs. 9. The method of claim 7 further comprising: demultiplexing said interleaved encoded bits to obtain said first portion and said second portion of said interleaved encoded bits. 10. The method of claim 7, wherein said bit interleaving said outer encoded bits includes: performing a first bit interleaving on a first portion of said outer encoded bits to obtain said first portion of said interleaved encoded bits; performing a second bit interleaving on a second portion of said outer encoded bits to obtain said second portion of said interleaved encoded bits. 11. The method of claim 7, wherein said performing the modified FQPSK modulation also includes: performing quadrature modulation on quadrature carrier signals using the I and Q waveform sequences to generate an output signal. 12. The method of claim 7 further comprising transmitting an output signal onto a channel, wherein the output signal is determined using the I and Q waveform sequences. 13. A method of encoding, comprising: bit interleaving a first portion of an input sequence of bits to produced interleaved bits; performing a modified FQPSK modulation on said interleaved bits and a second portion of the input sequence of bits to produce I and Q waveform sequences, wherein said performing the modified FQPSK modulation realizes a modulation with memory, wherein said performing the modified FQPSK modulation includes: performing a first recursive encoding on said interleaved bits to generate first encoder outputs; performing a second recursive encoding on said second portion of the input sequence to generate second encoder outputs; performing a signal mapping on the first encoder outputs and the second encoder outputs to generate said I and Q waveform sequences; wherein said I and Q waveform sequences are continuous in time. 14. The method of claim 13, wherein said performing the signal mapping generates the I waveform sequence based on the first encoder outputs and generates the Q waveform sequence based on the second encoder outputs. 15. The method of claim 13, wherein said performing the signal mapping generates the I waveform sequence based on the second encoder outputs and generates the Q waveform sequence based on the first encoder outputs. 16. The method of claim 13, wherein said performing the modified FQPSK modulation also includes: performing quadrature modulation on quadrature carrier signals using respectively the I and Q waveform sequences to generate an output signal. 17. The method of claim 13 further comprising transmitting an output signal onto a channel, wherein the output signal is determined using the I and Q waveform sequences. 18. An encoding system comprising: a first outer encoder configured to encode a first portion of an input sequence of bits to produce first outer encoded bits; a second outer encoder configured to encode a second portion of the input sequence of bits to produce second outer encoded bits; a first bit interleaver configured to perform bit interleaving on said first outer encoded bits to produce first interleaved encoded bits; a second bit interleaver configured to perform bit interleaving on said second outer encoded bits to produce second interleaved encoded bits; a modified FQPSK modulator configured to operate on said first interleaved encoded bits and said second interleaved encoded bits to produce I and Q waveform sequences, wherein said modified FQPSK modulator is configured to implement a modulation with memory, wherein said modified FQPSK modulator includes: an I-channel recursive encoder configured to encode the first interleaved encoded bits to generate I encoder outputs; a Q-channel recursive encoder configured to encode the second interleaved encoded bits to generate Q encoder outputs; a signal mapper configured to generate said I and Q waveform sequences based on the I encoder outputs and the Q encoder outputs; wherein said I and Q waveform sequences are continuous in time. 19. The system of claim 18, wherein said signal mapper is configured to generate the I waveform sequence based on the I encoder outputs and generate the Q waveform sequence based on the Q encoder outputs. 20. The system of claim 18, wherein said first and second outer encoders are linear encoders each with rate less than one. 21. The system of claim 18, wherein said first and second outer encoders are each repetition encoders. 22. The system of claim 18, wherein said modified FQPSK modulator also includes: a quadrature modulator configured to modulate quadrature carrier signals using the I and Q waveform sequences in order to generate an output signal. 23. The system of claim 18, wherein the system is configured to generate an output signal using the I and Q waveform sequences and to transmit the output signal onto a channel. 24. An encoding system comprising: an outer encoder configured to encode an input sequence of bits to produce outer encoded bits; a bit interleaver configured to bit interleave said outer encoded bits to produce interleaved encoded bits; and a modified FQPSK modulator configured to operate on said interleaved encoded bits to produce I and Q waveform sequences, wherein said modified FQPSK modulator is configured to implement a modulation with memory, wherein said modified FQPSK modulator includes: an I-channel recursive encoder configured to encode a first portion of said interleaved encoded bits to generate I encoder outputs; a Q-channel recursive encoder configured to encode a second portion of said interleaved encoded bits to generate Q encoder outputs; a signal mapper configured to generate said I and Q waveform sequences based on the I encoder outputs and the Q encoder outputs; wherein said I and Q waveform sequences are continuous in time. 25. The system of claim 24, wherein the signal mapper is configured to generate the I waveform sequence based on the I encoder outputs and generate the Q waveform sequence based on the Q encoder outputs. 26. The system of claim 24 further comprising a demultiplexer configured to demultiplex said interleaved encoded bits to obtain said first portion and said second portion of said interleaved encoded bits. 27. The system of claim 24, wherein said bit interleaver includes: a first bit interleaver configured to bit interleave a first portion of said outer encoded bits to obtain said first portion of said interleaved encoded bits; a second bit interleaver configured to bit interleave a second portion of said outer encoded bits to obtain said second portion of said interleaved encoded bits. 28. The system of claim 24, wherein the modified FQPSK modulator also includes a quadrature modulator configured to modulate quadrature carrier signals using the I and Q waveform sequences in order to generate an output signal. 29. The system of claim 24, wherein the system is configured to generate an output signal using the I and Q waveform sequences and to transmit the output signal onto a channel. 30. An encoding system comprising: a bit interleaver configured to bit interleave a first portion of an input sequence of bits to produced interleaved bits; a modified FQPSK modulator configured to operate on said interleaved bits and a second portion of the input sequence of bits to produce I and Q waveform sequences, wherein said modified FQPSK modulator is configured to implement a modulation with memory, wherein said modified FQPSK modulator includes: a first recursive encoder configured to encode said interleaved bits to generate first encoder outputs; a second recursive encoder configured to encode said second portion of the input sequence to generate second encoder outputs; a signal mapper configured to generate said I and Q waveform sequences based on the first encoder outputs and the second encoder outputs; wherein said I and Q waveform sequences are continuous in time. 31. The system of claim 30, wherein said signal mapper is configured to generate the I waveform sequence based on the first encoder outputs and generate the Q waveform sequence based on the second encoder outputs. 32. The system of claim 30, wherein said signal mapper is configured to generate the I waveform sequence based on the second encoder outputs and generate the Q waveform sequence based on the first encoder outputs. 33. The system of claim 30, wherein said modified FQPSK modulator also includes: a quadrature modulator configured to modulate quadrature carrier signals using the I and Q waveform sequences in order to generate an output signal. 34. The system of claim 30, wherein the system is configured to generate an output signal using the I and Q waveform sequences and to transmit the output signal onto a channel.
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