초록 ▼

A signal converter is comprised of a plurality of counters ("macro-counters"). In turn, each of the macro-counters is comprised of a plurality of single-bit counters ("micro-counters") that are adapted to receive configuration data in the form of bit fields. The configuration data is comprised of da

A signal converter is comprised of a plurality of counters ("macro-counters"). In turn, each of the macro-counters is comprised of a plurality of single-bit counters ("micro-counters") that are adapted to receive configuration data in the form of bit fields. The configuration data is comprised of data corresponding to a plurality of coefficients and of data for grouping the micro-counters into the macro-counters. The coefficients are derived from an input signal/output signal ratio of the converter, and control the manner by which the macro-counters generate the output signal. Thus the converter can be programmed by an end-user in the field.

대표청구항 ▼

What is claimed is: 1. A method for converting signals comprising: receiving a first value corresponding to a ratio between an input signal and an output signal, wherein the ratio is a non-integer; calculating a plurality of coefficients corresponding to the first value; creating a first set of dat

What is claimed is: 1. A method for converting signals comprising: receiving a first value corresponding to a ratio between an input signal and an output signal, wherein the ratio is a non-integer; calculating a plurality of coefficients corresponding to the first value; creating a first set of data comprised of data corresponding to the plurality of coefficients and of data for grouping a plurality of counters into a plurality of counter groups; and generating the output signal by using the plurality of counter groups, wherein a relationship between the input signal and the output signal is on average the ratio. 2. The method of claim 1 wherein the first set of data is bit field data. 3. The method of claim 1 wherein each of the plurality of counter groups is adapted to produce an output pulse for at least one predetermined number of input pulses in accordance with at least one of the plurality of coefficients. 4. The method of claim 1 wherein each of the plurality of counters is a single-bit counter, and wherein the first set of data is bit field data. 5. The method of claim 4 wherein creating the first set of data includes creating a plurality of binary values as a function of the plurality of coefficients, and wherein each group of the plurality of counter groups has associated therewith at least one of the plurality of coefficients, and wherein the number of counters in each group of the plurality of counter groups corresponds to a number of binary bits required to represent an integer value corresponding to the at least one of the plurality of coefficients. 6. The method of claim 5 wherein the plurality of counters in each of the plurality of counter groups are assembled in order of significant bits of at least one of the plurality of binary values. 7. The method of claim 1 wherein calculating the plurality of coefficients comprises: setting a first coefficient to be equal to an integer portion of the ratio; setting a second coefficient to be equal to one of the first coefficient plus 1 and the first coefficient minus 1; calculating a first error value according to a first deviation from the ratio by using only the first coefficient; calculating a second error value according to a second deviation from the ratio by using only the second coefficient; calculating a third coefficient as a function of the first error value and the second error value; and setting a fourth coefficient to be equal to one of the third coefficient plus 1 and the third coefficient minus one. 8. The method of claim 1 further comprising transmitting the first set of data to the plurality of counters. 9. The method of claim 8 wherein transmitting the first set of data includes transmitting the first set of data using a four-bit wide data bus. 10. The method of claim 9 wherein the data bus is chained between each of the plurality of counters such that on each clock signal of the data bus, one counter of the plurality of counters passes a portion of the first set of data to another counter of the plurality of counters located immediately downstream of the one counter. 11. The method of claim 1, wherein the plurality of counters are implemented in one of a complex programmable logic device (CPLD), a field programmable gate array (FPGA), and an application specific integrated circuit (ASIC). 12. A method for converting signals comprising: receiving a first value corresponding to a ratio between an input signal and an output signal, wherein the ratio is a non-integer; calculating a plurality of coefficients corresponding to the first value; creating a first set of data comprised of data corresponding to the plurality of coefficients and of data for grouping a plurality of counters into a plurality of counter groups, wherein each of the plurality of counter groups is adapted to produce an output pulse for at least one predetermined number of input pulses in accordance with at least one of the plurality of coefficients, wherein each of the plurality of counters is a single-bit counter, and wherein the first set of data is bit field data; and generating the output signal by using the plurality of counter groups, wherein a relationship between the input signal and the output signal is on average the ratio. 13. The method of claim 12 further comprising transmitting the first set of data to the plurality of counters. 14. The method of claim 12 wherein creating the first set of data includes creating a plurality of binary values as a function of the plurality of coefficients, and wherein each group of the plurality of counter groups has associated therewith at least one of the plurality of coefficients, and wherein the number of counters in each group of the plurality of counter groups corresponds to a number of binary bits required to represent an integer value corresponding to the at least one of the plurality of coefficients. 15. The method of claim 14 wherein the plurality of counters in each of the plurality of counter groups are assembled in order of significant bits of at least one of the plurality of binary values. 16. The method of claim 12 wherein calculating the plurality of coefficients comprises: setting a first coefficient to be equal to an integer portion of the ratio; setting a second coefficient to be equal to one of the first coefficient plus 1 and the first coefficient minus 1; calculating a first error value according to a first deviation from the ratio by using only the first coefficient; calculating a second error value according to a second deviation from the ratio by using only the second coefficient; calculating a third coefficient as a function of the first error value and the second error value; and setting a fourth coefficient to be equal to one of the third coefficient plus 1 and the third coefficient minus one. 17. A system for converting an input signal to an output signal, the system comprising: a processing unit capable of executing software routines; a logic circuit comprised of a plurality of counters; and programming logic executed by the processing unit, wherein the programming logic comprises: means for receiving a first value corresponding to a ratio between the input signal and the output signal, wherein the ratio is a non-integer; means for calculating a plurality of coefficients corresponding to the first value; and means for creating a first set of data comprised of data corresponding to the plurality of coefficients and of data for grouping the plurality of counters into a plurality of counter groups; and wherein the plurality of counter groups is adapted to generate the output signal, and wherein a relationship between the input signal and the output signal is on average the ratio. 18. The system of claim 17 wherein the system further comprises means for transmitting the first set of data to the plurality of counters. 19. The system of claim 17 wherein each of the plurality of counter groups is adapted to produce an output pulse for at least one predetermined number of input pulses in accordance with at least one of the plurality of coefficients. 20. The system of claim 17 wherein each of the plurality of counters is a single-bit counter, and wherein the first set of data is bit field data. 21. The system of claim 20 wherein the means for creating the first set of data includes means for creating a plurality of binary values as a function of the plurality of coefficients, wherein each group of the plurality of counter groups has associated therewith at least one of the plurality of coefficients, and wherein the number of counters in each group of the plurality of counter groups corresponds to a number of binary bits required to represent an integer value corresponding to the at least one of the plurality of coefficients. 22. The system of claim 21 wherein the plurality of counters in each of the plurality of counter groups are assembled in order of significant bits of at least one of the plurality of binary values. 23. The system of claim 17 wherein the means for calculating the plurality of coefficients comprises: means for setting a first coefficient to be equal to an integer portion of the ratio; means for setting a second coefficient to be equal to one of the first coefficient plus 1 and the first coefficient minus 1; means for calculating a first error value according to a first deviation from the ratio by using only the first coefficient; means for calculating a second error value according to a second deviation from the ratio by using only the second coefficient; means for calculating a third coefficient as a function of the first error value and the second error value; and means for setting a fourth coefficient to be equal to one of the third coefficient plus 1 and the third coefficient minus one. 24. The system of claim 17 wherein the logic circuit is comprised of one of a complex programmable logic device (CPLD), a field programmable gate array (FPGA), and an application specific integrated circuit (ASIC).