이 특허에 인용된 특허 (132)

1. Winters Kel D. (Moscow ID) Owsley Patrick A. (Moscow ID) French Catherine A. (Moscow ID) Bode Robert M. (Moscow ID) Feeley Peter S. (Moscow ID), Adaptive data compression system with systolic string matching logic.

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2. Dawes Robert L. (Allen TX), Adaptive processing system having an array of individually configurable processing components.

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3. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Grice Donald George ; Kogge Peter Michael ; Kuchinski David Christopher ; Knowles Billy Jack ; Lesmeis, Advanced parallel array processor (APAP).

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4. Dapp Michael Charles ; Dieffenderfer James Warren ; Miles Richard Ernest ; Nier Richard Edward ; Smoral Vincent John ; Stupp James Robert, Advanced parallel array processor computer package.

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5. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Grice Donald G. (Kingston NY) Kogge Peter M. (Endicott NY) Kuchinski Dav, Advanced parallel array processor(APAP).

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6. Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David , Advanced parallel processor including advanced support hardware.

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7. Cruickshank Ancil B. (Earlysville VA) Davis Richard K. (Crozet VA), Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respect.

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8. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and havin.

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9. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks including cascadable lookup tables.

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10. Nasserbakht Mitra ; Bosshart Patrick W., Bus interface buffer control in a microprocessor.

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11. Zlotnick Fredrick (Scottsdale AZ), Circuit and method of configuring a field programmable gate array.

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12. Nagler Werner (Hohenschaeftlarn DEX) Hlawa Fritz (Deisenhofen DEX) Schmidt Lothar (Fuerstenfeldbruck DEX), Circuit arrangement for telecommunications exchanges.

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13. Manning Troy A., Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times.

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14. Carlstedt L. Gunnar (Partille SEX), Computing device employing a reduction processor and implementing a declarative language.

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15. Kean Thomas A. (Edinburgh GB6), Configurable cellular array.

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16. Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.

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17. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.

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18. Carter William S. (Santa Clara CA), Configurable logic element.

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19. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.

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20. Hanrahan Shaila ; Phillips Christopher E., Configuration state memory for functional blocks on a reconfigurable chip.

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21. Shaila Hanrahan ; Christopher E. Phillips, Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit.

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22. Dani Y. Dakhil, DMA data streaming.

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23. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.

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24. Guest David H. (Balerno GBX), Daisy-chain bus system with truncation circuitry for failsoft bypass of defective sub-bus subsystem.

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25. Ardini ; Jr. Joseph L. (Needham MA) Beckwith Robert F. (Framingham MA) Chen Chi-Ping (Framingham MA) Rodman Paul K. (Ashland MA), Data processing system and method having an improved arithmetic unit.

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26. Kinerk Keith E. (Austin TX) Magliocco Joseph P. (Austin TX) Quan Hoang K. (Austin TX) Pena David A. (Austin TX), Data processor for executing a fuzzy logic operation and method therefor.

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27. Campbell Michael J. (Los Angeles CA) Finn Dennis J. (Los Angeles CA) Tucker George K. (Los Angeles CA) Vahey Michael D. (Manhattan Beach CA) Vedder Rex W. (Playa del Rey CA), Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and.

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28. Iwashita Masao (Tokyo JPX), Data-flow-type digital processing apparatus.

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29. Wang Hsinshih, Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups.

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30. Kemeny Sabrina E. (La Crescenta CA) Fossum Eric R. (La Crescenta CA) Nixon Robert H. (Shadow Hills CA), Digital parallel processor array for optimum path planning.

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31. Norman Richard S.,CAX ITX J0E 2K0, Direct replacement cell fault tolerant architecture.

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32. Garner Paul M. (The Woodlands TX) Boone Carrie (Houston TX) Cepulis Darren J. (Houston TX), Dynamically configurable portable computer system.

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33. DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.

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34. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.

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35. McCollum John L. (Saratoga CA), Field programmable digital signal processing array integrated circuit.

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36. Ebeling William H. C. (Seattle WA) Borriello Gaetano (Seattle WA), Field programmable gate array.

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37. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.

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38. Trimberger Stephen M., Field programmable gate array having programming instructions in the configuration bitstream.

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39. Ngai Kai-Kit (Allentown PA) Singh Satwant (Macungie PA), Field programmable gate array with multi-port RAM.

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40. Malhi Satwinder (Garland TX), Field reconfigurable logic/memory array.

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41. Kawata Tetsuro (Kanagawa JPX), Field-programmable gate array.

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42. Agrawal Om P. (Los Altos CA) Ilgenstein Kerry A. (Austin TX), Flexible synchronous/asynchronous cell structure for a high density programmable logic device.

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43. Holsztynski Wlodzimierz (Orlando FL), Geometric-arithmetic parallel processor.

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44. Ho Walford W. (Saratoga CA) Chen Chao-Chiang (Cupertino CA) Yang Yuk Y. (Foster City CA), Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array.

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45. Chatter Mukesh, High performance self modifying on-the-fly alterable logic FPGA, architecture and method.

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46. Young Steven P. ; Chaudhary Kamal ; Bapat Shekhar ; Krishnamurthy Sridhar ; Costello Philip D., High speed bus with tree structure for selecting bus driver.

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47. Vorbach, Martin; Munch, Robert, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.

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48. Allegrucci, Jean-Didier; Fox, Brian, Input/output architecture for efficient configuration of programmable input/output cells.

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49. Evan Shabtai (Saratoga CA) Sander Wendell B. (Los Gatos CA), Input/output section for an intelligent cell which provides sensing, bidirectional communications and control.

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50. Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.

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51. Lien Jung-Cheun ; Feng Sheng ; Sun Chung-yuan ; Huang Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.

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52. Lien, Jung-Cheun; Feng, Sheng; Sun, Chung-yuan; Huang, Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.

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53. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.

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54. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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55. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.

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56. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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57. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.

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58. Pechanek Gerald G. (Endwell NY) Vassiliadis Stamatis (Vestal NY) Delgado-Frias Jose G. (Vestal NY), Learning machine synapse processor system apparatus.

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59. Shaila Hanrahan ; Simon Guo, Loading data plane on reconfigurable chip.

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60. Bradley L. Taylor, Local memory unit system with global access for use on reconfigurable chips.

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61. Agrawal Om P. (Los Altos CA) Moench Jerry D. (Austin TX) Ilgenstein Kerry A. (Austin TX), Logic allocator for a programmable logic device.

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62. Steele Randy C. (Southlake TX), Logic block for programmable logic devices.

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63. Dani Y. Dakhil, Logic flag registers for monitoring processing system events.

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64. Galbraith Douglas C. (Fremont CA) El Gamal Abbas (Palo Alto CA) Greene Jonathan W. (Palo Alto CA), Logic module with configurable combinational and sequential blocks.

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65. Norman Richard S.,CAX ITX J0E 2K0, Massively-parallel processor array with outputs from individual processors directly to an external device without involv.

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66. Manning, Troy A., Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times.

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67. Horst Robert W. (Champaign IL), Memory system using linear array wafer scale integration architecture.

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68. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.

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69. Matter Eugene P. (Folsom CA) Sotoudeh Yahya S. (Santa Clara CA) Mathews Gregory S. (Boca Raton FL), Method and apparatus for independently stopping and restarting functional units.

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70. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for position independent reconfiguration in a network of multiple context processing elements.

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71. Hu King Seng (Penang MYX) Liew Vui Yong (Penang MYX), Method and apparatus for providing power saving modes to a pipelined processor.

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72. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for retiming in a network of multiple context processing elements.

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73. Agarwal Ramesh C. (Yorktown Heights NY) Groves Randall D. (Austin TX) Gustavson Fred G. (Briarcliff Manor NY) Johnson Mark A. (Austin TX) Olsson Brett (Round Rock TX), Method and system for dynamically reconfiguring a register file in a vector processor.

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74. Stearns Charles C. (San Jose CA) Kannappan Karthikeyan (San Jose CA), Method for 2-D affine transformation of images.

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75. Weisenborn Gerald M. (Ruckersville VA), Method for converting a programmable logic controller hardware configuration and corresponding control program for use o.

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76. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.

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77. Bozler Carl O. ; Drangmeister Richard G. ; Parr Robert J. ; Kushner Lawrence J., Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same.

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78. Kolchinsky Alexander (Andover MA), Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of da.

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79. Nosenchuck Daniel M. (Mercerville NJ) Littman Michael G. (Philadelphia PA), Multinode reconfigurable pipeline computer.

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80. Agrawal Om P. (San Jose CA) Landers George H. (Mountain View CA) Schmitz Nicholas A. (Cupertino CA) Moench Jerry D. (Austin TX) Ilgenstein Kerry A. (Austin TX), Multiple array high performance programmable logic device family.

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81. Judd James E. (Maple Shade NJ), Multiple function data processor.

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82. Okamoto Toshiya (Kyoto JPX) Miyata Souichi (Nara JPX), Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by.

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83. Markkula ; Jr. Armas C. ; Sander Wendell B. ; Evan Shabtai ; Smith Stephen B. ; Twitty William B., Network and intelligent cell for providing sensing, bidirectional communications and control.

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84. Naoaki Sudo JP; Satoshi Katagiri JP, Nonvolatile semiconductor memory device.

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85. Nosenchuck Daniel M. (Mercerville NJ), Optimizing compiler for computers.

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86. Watson James A. (Santa Clara CA) McClintock Cameron R. (Mountain View CA) Randhawa Hiten S. (Santa Clara CA) Li Ken M. (Santa Clara CA) Ahanin Bahram (Cupertino CA), PLD with selective inputs from local and global conductors.

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87. Kato Hideki (Kawasaki JPX) Yoshizawa Hideki (Kawasaki JPX) Iciki Hiroki (Kawasaki JPX) Masumoto Daiki (Kawasaki JPX), Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connec.

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88. Kato Hideki (Kawasaki JPX) Yoshizawa Hideki (Kawasaki JPX) Iciki Hiroki (Kawasaki JPX) Masumoto Daiki (Kawasaki JPX), Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data tra.

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89. Holsztynski Wlodzimierz (Mountainview CA) Benton Richard W. (Altamonte Springs FL) Johnson W. Keith (Goleta CA) McNamara Robert A. (Orlando FL) Naeyaert Roger S. (Plano TX) Noden Douglas A. (Orlando , Parallel data processor.

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90. Ewert Alfred P. (1088 Park Ave. New York NY 10022), Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments.

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91. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Parallel processing system having asynchronous SIMD processing.

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92. Morley Richard E. (Mason NH) Currie ; Jr. Douglas H. (Londonderry NH) Szakacs Gabor L. (Nashua NH), Parallel processor cell computer system.

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93. Hillis W. Daniel (Brookline MA), Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and.

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94. Magar Surender S. (Colorado Springs CO) Fleming Michael E. (Colorado Springs CO) Shen Shannon N. (Colorado Springs CO) Kishavy Kevin M. (Colorado Springs CO) Furman Christopher D. (Colorado Springs C, Pipelined combination and vector signal processor.

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95. Bock Gnther (Kmmersbruck DEX) Macht Helmut (Kmmersbruck DEX) Wombacher Christof (Amberg DEX) Prechtl Manfred (Nabburg DEX) Lengemann Andre (Edelsfeld DEX), Programmable control system including a logic module and a method for programming.

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96. Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.

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97. Mihara Tohru (Kanagawa) Narahara Mitsumasa (Kanagawa) Misawa Yasunao (Kanagawa) Wakamori Yasuo (Kanagawa) Yasunaga Shinichi (Kanagawa JPX), Programmable fuzzy logic circuits.

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98. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array device having cascaded means for function definition.

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99. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.

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100. Yamaura Shinichi (Takarazuka JPX) Yasui Takashi (Toyonaka JPX) Yoshioka Keiichi (Sanda JPX), Programmable logic array and data processing unit using the same.

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101. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.

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102. Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit incorporating a first-in first-out memory.

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103. Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA) Leong William (San Francisco CA), Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks.

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104. Pedersen Bruce B. (Santa Clara CA) Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Veenstra Kerry S. (Concord CA), Programmable logic array with local and global conductors.

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105. Ahanin Bahram (Cupertino CA) Balicki Janusz K. (San Jose CA) Kiani Khusrow (Oakland CA) Leong William (San Francisco CA) Li Ken-Ming (Santa Clara CA) Nouban Bezhad (Fremont CA), Programmable logic device having fast programmable logic array blocks and a central global interconnect array.

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106. Hung Lawrence C. (Los Gatos CA) Erickson Charles R. (Fremont CA), Programmable logic device including a parallel input device for loading memory cells.

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107. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.

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108. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.

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109. Stansfield Anthony I. (Hotwells GBX), Programmable logic device with memory that can store routing data of logic data.

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110. Thayer John S. (Spring TX) McGraw Montgomery C. (Spring TX), Programmable logic system for filtering commands to a microprocessor.

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111. Nabity Frederick A. (Lincoln NE) Wright Paul G. (Pleasant Dale NE) Hulinsky Raymond (Lincoln NE) Carson Douglas T. (Lincoln NE), Pumping system.

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112. Wada Masayoshi ; Asada Haruhiko H., Reconfigurable footprint mechanism for omnidirectional vehicles.

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113. Christopher E. Phillips ; Dale Wong ; Laurence H. Cooke, Reconfigurable logic for table lookup.

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114. Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining proc.

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115. Hanrahan Shaila ; Phillips Christopher E., Reconfigurable program sum of products generator.

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116. El Gamal Abbas (Palo Alto CA) Chiang Steve S. S. (Saratoga CA), Reconfigurable programmable interconnect architecture.

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117. Lin Chong Ming (Sunnyvale CA), Selective power-down for high performance CPU/system.

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118. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Sequencer for a time multiplexed programmable logic device.

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119. Morton Steven G. (Oxford CT), Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number.

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120. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Slide bus communication functions for SIMD/MIMD array processor.

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121. Poret Mark (Phoenix AZ), Software programmable logic array utilizing “and”and “or”gates.

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122. Zandveld Frederik (Hulsberg NLX) Wendt Matthias (Wurselen DEX) Janssens Marcel D. (Palo Alto CA), Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRA.

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123. Feeney James W. (Endicott NY) Jabusch John D. (Endwell NY) Lusch Robert F. (Vestal NY) Olnowich Howard T. (Endwell NY) Wilhelm ; Jr. George W. (Endwell NY), Switch network extension of bus architecture.

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124. Shiraishi Hajime,JPX, Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit usi.

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125. Frankle Jon A. (San Jose CA) Chene Mon-Ren (Cupertino CA), Timing driven method for laying out a user\s circuit onto a programmable integrated circuit device.

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126. Taylor Brad (Oakland CA), Video processing module using a second programmable logic device which reconfigures a first programmable logic device fo.

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127. Agarwal Anant (Framingham MA) Babb Jonathan (Ringgold GA) Tessier Russell (Cambridge MA), Virtual interconnections for reconfigurable logic systems.

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128. Agarwal Anant ; Babb Jonathan ; Tessier Russell, Virtual interconnections for reconfigurable logic systems.

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129. Kolchinsky Alexander (48 Gray Rd. Andover MA 01810), Virtual processor module including a reconfigurable programmable matrix.

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130. Subramanian,Ravi; Jha,Uma; Medlock,Joel D., Wireless spread spectrum communication platform using dynamically reconfigurable logic.

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131. Hiroshi Yamamoto JP, Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure.

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132. Athanas Peter ; Bittner ; Jr. Ray A., Worm-hole run-time reconfigurable processor field programmable gate array (FPGA).

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