Process for transferring a layer of strained semiconductor material
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/46
H01L-021/02
H01L-021/30
출원번호
US-0165339
(2005-06-24)
등록번호
US-7338883
(2008-03-04)
우선권정보
FR-02 08602(2002-07-09)
발명자
/ 주소
Ghyselen,Bruno
Bensahel,Daniel
Skotnicki,Thomas
출원인 / 주소
S.O.I.Tec Silicon on Insulator Technologies
대리인 / 주소
Winston & Strawn LLP
인용정보
피인용 횟수 :
2인용 특허 :
19
초록▼
The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter
The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.
대표청구항▼
What is claimed is: 1. A method of preparing a semiconductor wafer, comprising: providing a repeating pattern of first and second layers of semiconductor material, with at least two first layers separated by at least one second layer; performing multiple transfers of portions of the pattern to rece
What is claimed is: 1. A method of preparing a semiconductor wafer, comprising: providing a repeating pattern of first and second layers of semiconductor material, with at least two first layers separated by at least one second layer; performing multiple transfers of portions of the pattern to receiving substrates to produce product wafers, each portion including at least one of the first layers, wherein one of the first layers is transferred to a first receiving wafer in a first transfer step, and another first layer is transferred to a second receiving wafer in a second transfer step. 2. The method of claim 1, further comprising: creating regions of weakness in the second layers to facilitate splitting; and splitting the pattern at the second layers for transferring the first layers. 3. The method of claim 2, wherein at least one of the regions of weakness is created by implanting atomic species. 4. The method of claim 3, wherein all of the regions of weakness are created by implanting atomic species. 5. The method of claim 1, wherein the pattern comprises first and second layer groups, each comprising first and second layers in substantially a same order, the first layers having substantially a same first configuration, and the second layers having substantially a same second configuration that is different from the first configuration. 6. A method of preparing a semiconductor wafer, comprising: providing a repeating pattern of first and second layers; and performing multiple transfers of portions of the pattern to receiving substrates to produce product wafers, each portion including at least one of the first layers; wherein the repeating pattern of first and second layers is obtained by: providing a matching substrate that has a matching layer with a first lattice parameter on a first surface; growing on the first surface of the matching layer a first strained layer of a first semiconductor material in a strained state having the same first lattice parameter as in the matching layer; providing a first strain-retaining layer having the first lattice parameter on the first strained layer for maintaining strain from the side of the first strained layer opposite the matching layer; and growing a second strained layer of semiconductor material having the first lattice parameter on the first strain-retaining layer; and wherein the transfers are made by creating a second region of weakness in the first strain-retaining layer; associating a second receiving substrate with the strained layers to form a second composite structure; and obtaining a second product wafer and a second donor wafer by splitting the second composite structure at the second region of weakness, wherein the second product wafer includes the second strained layer and the second receiving substrate, while the second donor wafer includes at least a portion of the first strain-retaining layer; creating a first region of weakness in the matching substrate; associating a first receiving substrate with the first strained layer to form a first composite structure; and obtaining a first product wafer and a first donor wafer by splitting the first composite structure at the first region of weakness, wherein the first product wafer includes the first strained layer and the first receiving substrate, while the first donor wafer includes at least a portion of the matching layer; wherein the first layers of the repeating pattern comprise the strained layers, and the second layers of the repeating pattern comprise the strain retaining layers. 7. The method of claim 6, wherein the first region of weakness is created in the second donor wafer. 8. The method of claim 6, further comprising providing a second strain-retaining layer on the second strained layer and having the first lattice parameter for maintaining the strained state of the second strained layer from the side of the second strained layer opposite the first strain-retaining layer. 9. The method of claim 8, wherein the pattern comprises first and second layer groups, wherein each of the groups have substantially a same arrangement of first and second layers. 10. The method of claim 9, wherein each group has only one first layer. 11. The method of claim 6, wherein the matching layer includes a buffer layer and a relaxed surface layer on which the first strained layer is grown. 12. The method of claim 11, wherein the lattice parameter of the buffer layer is graded between the first and second lattice parameters. 13. The method of claim 6, wherein the first strained layer is strained for modifying the energy band structure of the semiconductor material of that layer for improving the electrical properties thereof compared to the semiconductor material in a relaxed state. 14. The method of claim 13, wherein the first strained layer has a thickness that is less than the critical thickness thereof for preventing substantial relaxation of strain. 15. The method of claim 14, wherein first strained layer has a thickness of less than about 20 nanometers prior to the splitting. 16. The method of claim 14, wherein the first strained layer has a charge carrier mobility that is at least about 50% higher than in the semiconductor material in a relaxed state. 17. The method of claim 6, wherein the strained layers comprises silicon, and the matching layer comprises silicon germanium. 18. The method of claim 17, further comprising thickening the strained layers of silicon epitaxially after the respective splitting. 19. The method of claim 18, wherein the strained layers are thickened epitaxially after the respective splitting to a layer thickness of greater than about 40 nm.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (19)
Kub Francis J. ; Hobart Karl D., Fabrication ultra-thin bonded semiconductor layers.
Gosele, Ulrich; Plossl, Andreas, Method for the manufacture of a substrate, substrate manufactured in accordance with this method, carrier wafer and diamond jewel.
Barge,Thierry; Auberton Herve,Andr챕; Aga,Hiroji; Tate,Naoto, Method for treating substrates for microelectronics and substrates obtained according to said method.
Hiroji Aga JP; Naoto Tate JP; Kiyoshi Mitani JP, Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method.
Bin Yu ; William G. En ; Judy Xilin An ; Concetta E. Riccobene, Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer.
Godbey David J. (Bethesda MD) Hughes Harold L. (West River MD) Kub Francis J. (Severna Park MD), Method of producing a thin silicon-on-insulator layer.
Canaperi, Donald F.; Chu, Jack Oon; D'Emic, Christopher P.; Huang, Lijuan; Ott, John Albrecht; Wong, Hon-Sum Philip, Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.