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Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
  • H01L-021/02
출원번호 US-0690084 (2003-10-20)
등록번호 US-7338908 (2008-03-04)
발명자 / 주소
  • Koos,Daniel A.
  • Mayer,Steven T.
  • Park,Heung L.
  • Cleary,Timothy Patrick
  • Mountsier,Thomas
출원인 / 주소
  • Novellus Systems, Inc.
대리인 / 주소
    Beyer Weaver, LLP
인용정보 피인용 횟수 : 30  인용 특허 : 39

초록

An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the s

대표청구항

What is claimed is: 1. A method of depositing a metal-containing capping layer on metal portions of a substrate containing a layer of metal and dielectric, the method comprising: (a) receiving the substrate containing the layer of metal and dielectric; (b) wet etching metal from the substrate from

이 특허에 인용된 특허 (39)

  1. Chen LinLin, Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece.
  2. Watts David ; Bajaj Rajeev ; Das Sanjit ; Farkas Janos ; Dang Chelsea ; Freeman Melissa ; Saravia Jaime A. ; Gomez Jason ; Cook Lance B., Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture.
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  6. Park, Chi-kyun; Kakirde, Archana; Liu, Peikang; Manivannan, Venkatesan; Chai, Chul; Ihm, Dong-joon; Lee, Jon-ha; Roh, Kwon-sun, Composition for forming electrode active material of lithium secondary battery, composition for forming separator and method of preparing lithium secondary battery using the compositions.
  7. Bickford Harry R. (Ossining NY) Canfield Dennis A. (Montrose PA) Graham Arthur E. (Lexington KY) Tisdale Stephen L. (Vestal NY) Viehbeck Alfred (Stormville NY), Conditioning of a substrate for electroless plating thereon.
  8. Chen, Shyng-Tsong; Dalton, Timothy J.; Davis, Kenneth M.; Hu, Chao-Kun; Jamin, Fen F.; Kaldor, Steffen K.; Krishnan, Mahadevaiyer; Kumar, Kaushik; Lofaro, Michael F.; Malhotra, Sandra G.; Narayan, Ch, Copper recess process with application to selective capping and electroless plating.
  9. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  10. Shacham-Diamand Yosi ; Nguyen Vinh ; Dubin Valery, Electroless deposition of metal films with spray processor.
  11. Chebiam, Ramanan V.; Dubin, Valery M., Electroless plating bath composition and method of using.
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  14. Hsu, Wei-Yung; Chen, Liang-Yuh; Morad, Ratson; Carl, Daniel A., Method for dishing reduction and feature passivation in polishing processes.
  15. Dubin Valery ; Ting Chiu, Method for fabricating copper-aluminum metallization.
  16. Shue, Shau-Lin; Liang, Mong-Song, Method for forming a self-passivated copper interconnect structure.
  17. Cooper,Emanuel; Furman,Bruce; Rath,David, Method for isotropic etching of copper.
  18. Cohen Abraham B. (Springfield NJ) Fan Roxy N. (E. Brunswick NJ) Quinn John A. (Morganville NJ), Method for making multilayer circuits using embedded catalyst receptors.
  19. Feldstein Nathan (Princeton NJ), Method for rendering non-platable surfaces platable.
  20. Hasegawa Makiko,JPX ; Toyoda Yoshihiko,JPX ; Mori Takeshi,JPX ; Fukada Tetsuo,JPX, Method of making embedded wiring system.
  21. Arledge John K. (Ft. Lauderdale FL) Swirbel Thomas J. (Davie FL) Barreto Joaquin (Coral Springs FL), Method of metallizing high aspect ratio apertures.
  22. Shang, Quanyuan; White, John M.; Bachrach, Robert Z.; Law, Kam S., Methods to form metal lines using selective electrochemical deposition.
  23. Cheng,Chin Chang; Dubin,Valery M., Multiple stage electroless deposition of a metal layer.
  24. Kaja Suryanarayana (Hopewell Junction NY) Mukherjee Shyama P. (Hopewell Junction NY) O\Sullivan Eugene J. (Upper Nyack NY) Paunovic Milan (Port Washington NY), Palladium sulfate solution for the selective seeding of the metal interconnections on polyimide dielectrics for electrol.
  25. Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
  26. Sasaki Yasutaka,JPX ; Hayasaka Nobuo,JPX ; Kaneko Hisashi,JPX ; Hirabayashi Hideaki,JPX ; Higuchi Masatoshi,JPX, Polishing agent and polishing method using the same.
  27. Yuan Benzhen,JPX ; Asai Motoo,JPX, Pretreating solution for electroless plating, electroless plating bath and electroless plating process.
  28. Nuzzi Francis J. (Lynbrook NY) Leech Edward J. (Oyster Bay NY) Charm Richard W. (Glen Cove NY) Polichette Joseph (South Farmingdale NY), Process and composition for sensitizing articles for metallization.
  29. Kaja Suryanarayana (Hopewell Junction NY) O\Sullivan Eugene J. (Nyack NY) Schrott Alejandro G. (New York NY), Process for fabricating improved multilayer interconnect systems.
  30. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  31. Paunovic Milan ; Jahnes Christopher, Production of electroless Co(P) with designed coercivity.
  32. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  33. Dubin Valery ; Ting Chiu ; Cheung Robin W., Pulse electroplating copper or copper alloys.
  34. Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
  35. Contolini Robert J. (Pleasanton CA) Mayer Steven T. (San Leandro CA) Tarte Lisa A. (Livermore CA), Removal of field and embedded metal by spin spray etching.
  36. Cohen Uri, Seed layers for interconnects and methods for fabricating such seed layers.
  37. Andricacos,Panayotis C.; Chen,Shyng Tsong; Cotte,John M.; Deligianni,Hariklia; Krishnan,Mahadevaiyer; Tseng,Wei Tsu; Vereecken,Philippe M., Selective capping of copper wiring.
  38. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
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이 특허를 인용한 특허 (30)

  1. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  2. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  3. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  4. Reid, Jonathan D.; Webb, Eric G.; Minshall, Edmund B.; Kepten, Avishai; Stowell, R. Marshall; Mayer, Steven T., Capping before barrier-removal IC fabrication method.
  5. Outka, Duane; Augustino, Jason; Avoyan, Armen; Whitten, Stephen; Shih, Hong; Fang, Yan, Cleaning of bonded silicon electrodes.
  6. Mayer, Steven T.; Koos, Daniel A.; Webb, Eric, Fabrication of semiconductor interconnect structure.
  7. Mayer, Steven T.; Koos, Daniel A.; Webb, Eric, Fabrication of semiconductor interconnect structure.
  8. Aubel, Oliver; Hasse, Wolfgang; Hommel, Martina; Koerner, Heinrich, Long-term heat-treated integrated circuit arrangements and methods for producing the same.
  9. Andreyushchenko,Tatyana N.; Cadien,Kenneth; Fischer,Paul; Dubin,Valery M., Method to fabricate interconnect structures.
  10. Boyanov, Boyan; Singh, Kanwal Jit, Methods and apparatuses to form self-aligned caps.
  11. Boyanov, Boyan; Singh, Kanwal Jit, Methods and apparatuses to form self-aligned caps.
  12. He, Hong; Li, Juntao; Wang, Junli; Yang, Chih-Chao, Microstructure of metal interconnect layer.
  13. Mayer, Steven T.; Porter, David W., Modulated metal removal using localized wet etching.
  14. Chang, Song-Yuan; Ho, Ming-Che; Lu, Ming-hui, Polishing composition for planarizing metal layer.
  15. Shih, Chien-Hsueh; Tsai, Minghsing; Yu, Chen-Hua; Yeh, Ming-Shih, Process for improving copper line cap formation.
  16. Shih, Chien-Hsueh; Tsai, Minghsing; Yu, Chen-Hua; Yeh, Ming-Shih, Process for improving copper line cap formation.
  17. Dordi, Yezdi; Boyd, John; Arunagiri, Tiruchirapalli; Redeker, Fritz C.; Thie, William; Howald, Arthur M., Processes and systems for engineering a copper surface for selective metal deposition.
  18. Mayer, Steven T.; Porter, David W., Reduced isotropic etchant material consumption and waste generation.
  19. Mayer, Steven T.; Porter, David W., Reduced isotropic etchant material consumption and waste generation.
  20. Preusse, Axel; Nopper, Markus; Ortleb, Thomas; Boemmels, Juergen, Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices.
  21. Bailey, Carla A.; Bowne, Camille P.; Semkow, Krystyna W., Selective etch of TiW for capture pad formation.
  22. Zhang, Tianhong; Ditali, Akram, Semiconductor constructions.
  23. Zhang, Tianhong; Ditall, Akram, Semiconductor constructions.
  24. Zhang, Tianhong; Ditali, Akram, Semiconductor constructions, semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers.
  25. Zhang, Tianhong; Ditali, Akram, Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers.
  26. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
  27. Kang, Shin-Jae; Oh, Gyuhwan; Park, Insun; Lim, Hyunseok; Lim, Nak-Hyun, Variable resistance non-volatile memory cells and methods of fabricating same.
  28. Mayer, Steven T.; Webb, Eric G.; Porter, David W., Wet etching methods for copper removal and planarization in semiconductor processing.
  29. Mayer, Steven T.; Webb, Eric; Porter, David W., Wet etching methods for copper removal and planarization in semiconductor processing.
  30. Mayer, Steven T.; Webb, Eric; Porter, David W., Wet etching methods for copper removal and planarization in semiconductor processing.
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