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Retrograde trench isolation structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0919546 (2004-08-16)
등록번호 US-7339253 (2008-03-04)
발명자 / 주소
  • Tsai,Chao Tzung
  • Wang,Ling Sung
  • Yen,Ching Lang
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company
대리인 / 주소
    Duane Morris LLP
인용정보 피인용 횟수 : 7  인용 특허 : 40

초록

Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidation, such tha

대표청구항

What is claimed is: 1. A trench structure, comprising: a semiconductor substrate having a trench therein; said trench having a first portion, a second portion and walls, the second portion having a larger dimension than the first portion; and said trench having a layer of silicon oxide on the walls

이 특허에 인용된 특허 (40)

  1. Chen Chao-Cheng,TWX, Bottom rounding in shallow trench etching using a highly isotropic etching step.
  2. Marty,Michel; Fortuin,Arnoud; Arnal,Vincent, Deep insulating trench.
  3. Miller, Alan J.; Soesilo, Fandayani, In situ and ex situ hardmask process for STI with oxide collar application.
  4. Paul A. Farrar, Low dielectric constant shallow trench isolation.
  5. Chuan Lin ; Thomas Schafbauer ; Paul Wensley, Method and structure for shallow trench isolation.
  6. Tammy Zheng ; Calvin Todd Gabriel ; Edward K. Yeh, Method for a consistent shallow trench etch profile.
  7. Wei Chi-Hung,TWX, Method for aligning shallow trench isolation.
  8. Lee, Jae-kyu, Method for fabricating a semiconductor device reducing junction leakage current and narrow width effect.
  9. Uhlig, Ines; Zimmermann, Jens; Wege, Stephan, Method for fabricating a trench isolation for electrically active components.
  10. Won Soung Park KR; Phil Goo Kong KR; Ho Seok Lee KR; Dong Duk Lee KR, Method for fabricating semiconductor device by using etching polymer.
  11. Kishimoto Koji,JPX, Method for forming a shallow trench isolation structure.
  12. Stephan Bradl DE; Olaf Heitzsch DE; Michael Schmidt DE, Method for forming a trench structure in a silicon substrate.
  13. Hsu, Jen-Tian; Tang, Wen-Hsiang, Method for forming an STI feature to avoid acidic etching of trench sidewalls.
  14. Chung, Yi Sun, Method for forming an isolation region in a semiconductor device.
  15. Joo, Joon-Yong, Method for forming isolation trench.
  16. Liaw Jhon-Jhy,TWX ; Lee Jin-Yuan,TWX, Method for forming shallow trench isolation.
  17. Shye-Lin Wu TW, Method for forming trench isolation regions.
  18. Sakai Maiko,JPX ; Kuroi Takashi,JPX ; Horita Katsuyuki,JPX, Method for manufacturing an isolation trench having plural profile angles.
  19. Lee Ki-Yeup,KRX ; Kang Byoung-Ju,KRX, Method for manufacturing shallow trench isolation in semiconductor device.
  20. Hong Gary,TWX, Method for manufacturing shallow trench isolation structure including a dual trench.
  21. Philipossian Ara (Redwood Shores CA) Soleimani Hamid R. (Westborough MA) Doyle Brian S. (Framington MA), Method of decreasing the field oxide etch rate in isolation technology.
  22. Liu Guan-Jiun,TWX ; Chen Shih-Ching,TWX ; Sung Chi-Jui,TWX ; Hsu Chung-Po,TWX, Method of forming a shallow trench isolation structure.
  23. Lee Kan-Yuan,TWX ; Ko Joe,TWX ; Fang Yang-Hui,TWX ; Hong Gary,TWX, Method of forming shallow trench isolation.
  24. Lou Chine-Gie,TWX, Method of forming shallow trench isolation structure.
  25. Yew Tri-Rung,TWX ; Huang Kuo-Tai,TWX ; Yang Gwo-Shii,TWX ; Lur Water,TWX, Method of manufacturing shallow trench isolation.
  26. Kamath, Arvind; Gopinth, Venkatesh P., Method of shallow trench isolation formation and planarization.
  27. Ellie Yieh ; Li-Qun Xia ; Srinivas Nemani, Methods and apparatus for shallow trench isolation.
  28. Davies, Robert Bruce, Monolithic low dielectric constant platform for passive components and method.
  29. Lin Chrong Jung,TWX ; Chen Shui-Hung,TWX ; Shih Jiaw-Ren,TWX, STI process for improving isolation for deep sub-micron application.
  30. Hongyong Zhang JP, Semiconductor device and process for fabricating the same.
  31. Ishitsuka, Norio; Miura, Hideo; Ikeda, Shuji; Yoshida, Yasuko; Suzuki, Norio; Watanabe, Kozo; Kanamitsu, Kenji, Semiconductor device having element isolation structure.
  32. Ma Yi ; Shive Scott F. ; Brown Melissa M., Semiconductor device, trench isolation structure and methods of formations.
  33. Hong Gary,TWX, Shallow trench isolation for semiconductor devices.
  34. Singh, Kailash N., Shallow trench isolation method for forming rounded bottom trench corners.
  35. Arthanari, Senthilkumar; Mei, Shaw-Ning; Vishnesky, Edward J., Shallow trench isolation using non-conformal dielectric and planarizatrion.
  36. Cheng-Ku Chen TW; Fang-Cheng Chen TW; Hun-Jan Tao TW, Silicon shallow trench etching with round top corner by photoresist-free process.
  37. Wylie, Ian, Transistor device having an isolation structure located under a source region, drain region and channel region and a method of manufacture thereof.
  38. Park Tai-su,KRX ; Park Moon-han,KRX ; Park Kyung-won,KRX ; Lee Han-sin,KRX, Trench isolation structure, semiconductor device having the same, and trench isolation method.
  39. Xu, Daniel; Bengu, Erman; Jin, Ming, Trench sidewall profile for device isolation.
  40. Li, Wei Ning; Lin, Yung Tao, Trench transistor structure and formation method.

이 특허를 인용한 특허 (7)

  1. Shank, Steven M.; Vaughn, Daisy; Doan, Thai, Deep trench isolation structures.
  2. Cai, Jin; Cheng, Kangguo; Khakifirooz, Ali; Kerber, Pranita, Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same.
  3. Lee, Yu Jin, Semiconductor device and method for fabricating the same.
  4. Furukawa, Toshiharu; Robison, Robert R.; Williams, Richard Q., Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure.
  5. Furukawa, Toshiharu; Robison, Robert R.; Williams, Richard Q., Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure.
  6. Liaw, Jhon-Jhy; Chen, Chao-Cheng; Chang, Chia-Wei, Shallow trench isolation with improved structure and method of forming.
  7. Liaw, Jhon-Jhy; Chen, Chao-Cheng; Chang, Chia-Wei, Shallow trench isolation with improved structure and method of forming.
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