Electrostatic discharge protection circuit having a ring oscillator timer circuit
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02H-003/22
H02H-003/20
출원번호
US-0128373
(2002-04-24)
등록번호
US-7339770
(2008-03-04)
발명자
/ 주소
Maloney,Timothy J.
Poon,Steven S.
출원인 / 주소
Intel Corporation
대리인 / 주소
Schwegman, Lundberg & Woessner, P.A.
인용정보
피인용 횟수 :
8인용 특허 :
22
초록▼
An electrostatic discharge protection circuit is provided having a first electrically conductive element (such as a current sinking transistor) to couple between a power source and a first node. The first electrically conductive element has a control input terminal. A discharge path control circuit
An electrostatic discharge protection circuit is provided having a first electrically conductive element (such as a current sinking transistor) to couple between a power source and a first node. The first electrically conductive element has a control input terminal. A discharge path control circuit having an output terminal couples to the control input terminal of the first electrically conductive element. A timer circuit having an output terminal couples to the input terminal of the discharge path control circuit. A ring oscillator timer circuit having an output terminal couples to an input terminal of the timer circuit. The ring oscillator timer circuit may include a series of inverter circuits and/or counter circuits (such as flip-flop circuits).
대표청구항▼
What is claimed is: 1. A circuit comprising: a current sinking device having a first control terminal; a control circuit including a transistor and a capacitor and having an output terminal coupled to the first control terminal of said current sinking device; and a ring oscillator timer circuit to
What is claimed is: 1. A circuit comprising: a current sinking device having a first control terminal; a control circuit including a transistor and a capacitor and having an output terminal coupled to the first control terminal of said current sinking device; and a ring oscillator timer circuit to couple to a control terminal of said control circuit, wherein the ring oscillator timer circuit is coupled to a gate of said transistor, the ring oscillator timer circuit includes a number of ring oscillator stages, and the transistor has a resistance proportional to the number of ring oscillator stages. 2. The circuit of claim 1, wherein the ring oscillator timer circuit includes at least ten inverter circuits coupled in series. 3. The circuit of claim 1, wherein said ring oscillator timer circuit comprises a series of inverter circuits. 4. The circuit of claim 3, wherein said ring oscillator timer circuit further comprises a logic circuit to perform a logical NAND operation based on input signals. 5. The circuit of claim 4, wherein inputs of said logic circuit are to couple between outputs of adjacent inverter circuits, and said logic circuit to perform a logical NAND operation on said input signals received on said inputs. 6. The circuit of claim 1, wherein said current sinking device comprises at least one transistor. 7. The circuit of claim 6, wherein an input to said ring oscillator timer circuit is to couple to a gate of said at least one transistor. 8. The circuit of claim 1, wherein said ring oscillator timer circuit comprises at least one counter circuit. 9. The circuit of claim 8, wherein said at least one counter circuit comprises a flip-flop circuit. 10. An integrated circuit comprising an electrostatic discharge protection circuit having a ring oscillator timer circuit, the ring oscillator timer circuit having an output coupled to a timer circuit, the timer circuit including a transistor and a capacitor, wherein the output coupled to the timer circuit provides a signal at a gate of the transistor, wherein the transistor has a resistance proportional to an area used for the ring oscillator circuit, wherein said electrostatic discharge protection circuit comprises a power supply clamp having a current sinking device to couple a power supply terminal and a first node in response to an electrostatic event. 11. The integrated circuit of claim 10, wherein said first node comprises ground. 12. The integrated circuit of claim 10, wherein said current sinking device comprises a transistor. 13. An integrated circuit comprising an electrostatic discharge protection circuit having a ring oscillator timer circuit, the ring oscillator timer circuit having an output coupled to a timer circuit, the timer circuit including a transistor and a capacitor, wherein the output coupled to the timer circuit provides a signal at a gate of the transistor, wherein the transistor has a resistance proportional to an area used for the ring oscillator circuit, wherein said electrostatic discharge protection circuit comprises a power supply clamp having a first current sinking device to couple a power supply terminal and a first node during an electrostatic event and a second current sinking device to couple said first node and a second node in response to said electrostatic event. 14. The integrated circuit of claim 13, wherein said first node comprises a first intermediate node and said second node comprises ground. 15. The integrated circuit of claim 13, further comprising internal circuitry to perform a desired function. 16. An electrostatic discharge protection circuit comprising: a first electrically conductive element to couple between a power source and a first node, the first electrically conductive element having a control input terminal; a discharge path control circuit having an output terminal to couple to the control input terminal of the first electrically conductive element; a timer circuit including a transistor and a capacitor and having an output terminal to couple to the input terminal of said discharge path control circuit; and a ring oscillator timer circuit having an output terminal to couple to an input terminal of said timer circuit, the ring oscillator timer circuit coupled to a gate of the transistor, wherein said discharge path control circuit comprises a first inverting circuit stage having an input terminal to couple to the output terminal of said timer circuit and an output terminal, and a second inverting circuit stage having an output terminal to couple to the control input terminal of said first electrically conductive element and an input terminal to couple to the output terminal of said first inverting circuit stage. 17. The electrostatic discharge protection circuit of claim 16, wherein said ring oscillator timer circuit provides a signal at the gate of said transistor. 18. The electrostatic discharge protection circuit of claim 16, wherein said ring oscillator timer circuit comprises a series of inverter circuits. 19. The electrostatic discharge protection circuit of claim 18, wherein said ring oscillator timer circuit further comprises a first logic circuit to perform a logical NAND operation based on input signals. 20. The electrostatic discharge protection circuit of claim 19, wherein inputs of said first logic circuit are to couple between outputs of adjacent inverter circuits, and said first logic circuit to perform a logical NAND operation on said input signals received on said inputs. 21. The electrostatic discharge protection circuit of claim 16, wherein said first electrically conductive element comprises at least one transistor. 22. The electrostatic discharge protection circuit of claim 21, wherein an input to said ring oscillator timer circuit is to couple to a gate of said at least one transistor. 23. The electrostatic discharge protection circuit of claim 16, wherein said ring oscillator timer circuit comprises at least one counter circuit. 24. The electrostatic discharge protection circuit of claim 23, wherein said at least one counter circuit comprises a flip-flop circuit. 25. The electrostatic discharge protection circuit of claim 16, wherein said first node comprises ground. 26. The electrostatic discharge protection circuit of claim 16, further comprising a second electrically conductive element between said first node and a second node, the second electrically conductive element having a control input terminal to couple to said second node. 27. The electrostatic discharge protection circuit of claim 26, further comprising a third electrically conductive element between said second node and a third node, said third electrically conductive element having a control input terminal to couple to said third node. 28. A system comprising: a voltage supply; circuitry to be powered by said voltage supply and perform a desired function; an electrostatic discharge protection circuit including: a current sinking device having a first control terminal; a control circuit including a transistor and a capacitor and having an output terminal coupled to the first control terminal of said current sinking device; and a ring oscillator timer circuit to couple to a control terminal of said control circuit, the ring oscillator timer circuit coupled to a gate of the transistor, the ring oscillator timer circuit includes a number of ring oscillator stages, and the transistor has a resistance proportional to the number of ring oscillator stages. 29. The system of claim 28, wherein said circuitry and said electrostatic discharge protection circuit are provided on an integrated circuit. 30. The system of claim 28, wherein said ring oscillator timer circuit provides a signal at the gate of said transistor.
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