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A nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagne

A nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a changeable magnetization state, and a second ferromagnetic layer with a non-changeable magnetization state. A current of spin polarized electrons has a magnitude which can be varied so that a data value can be stored in the memory element by varying a relative orientation of the two ferromagnetic layer. An output of the device is coupled to a conventional CMOS amplifier to determine such relationship.

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What is claimed is: 1. A hybrid magnetoelectronic spin-based memory cell comprising: a memory element configured to transport a current of spin polarized electrons including: i) a first ferromagnetic layer with a first magnetization state; ii) a second ferromagnetic layer with a second magnetizatio

What is claimed is: 1. A hybrid magnetoelectronic spin-based memory cell comprising: a memory element configured to transport a current of spin polarized electrons including: i) a first ferromagnetic layer with a first magnetization state; ii) a second ferromagnetic layer with a second magnetization state; wherein a magnitude of said current of spin polarized electrons varies in accordance with a relationship between said first magnetization state and said second magnetization state and further corresponds to a data value stored in the hybrid magnetoelectronic spin-based memory cell; an isolation element coupled to an output of said electron spin-based memory element and adapted to isolate said data value, said isolation element including a semiconductor based transistor; a complementary metal oxide semiconductor (CMOS) sensing circuit coupled to said output and which is adapted to determine said data value based on said magnitude of said current of spin polarized electrons. 2. The hybrid magnetoelectronic spin-based memory cell of claim 1, wherein said memory element is situated above said semiconductor based transistor and is separated by an insulation layer. 3. The hybrid magnetoelectronic spin-based memory cell of claim 1, wherein an impedance of the memory element is on the order of 1 ohm. 4. The hybrid magnetoelectronic spin-based memory cell of claim 1 wherein said memory element is part of a memory array. 5. The hybrid magnetoelectronic spin-based memory cell of claim 4 wherein said memory element is coupled in parallel by a read line to a second memory element. 6. The hybrid magnetoelectronic spin-based memory cell of claim 1 further including a low transmission barrier located between said first ferromagnetic layer and said second ferromagnetic layer. 7. The hybrid magnetoelectronic spin-based memory cell of claim 1, wherein said isolation element is coupled to a bit line, and further including a second semiconductor based transistor isolation element coupling said electron spin-based memory element to a bit reference line. 8. The hybrid magnetoelectronic spin-based memory cell of claim 1 wherein the semiconductor-based transistor is a field effect transistor (FET). 9. The hybrid magnetoelectronic spin-based memory cell of claim 1, further including a read line coupled to read data from said memory element, and at least one separate write line coupled to write data to said memory element. 10. The hybrid magnetoelectronic spin-based memory cell of claim 9, wherein said write line uses a single polarity current pulse. 11. The hybrid magnetoelectronic spin-based memory cell of claim 9, wherein said write line includes two partially overlapping write lines. 12. The hybrid magnetoelectronic spin-based memory cell of claim 11, wherein said memory element only changes state when a current pulse is present on both of said two overlapping write lines. 13. The hybrid magnetoelectronic spin-based memory cell of claim 11, wherein at least one of said write lines is arranged perpendicular to said read line. 14. The hybrid magnetoelectronic spin-based memory cell of claim 1, wherein said first ferromagnetic layer and said second ferromagnetic layer each include at least two separate layers. 15. The hybrid magnetoelectronic spin-based memory cell of claim 1, wherein both a current pulse and a voltage pulse are used to read data stored by said electron spin-based memory element. 16. A hybrid magnetoelectronic spin-based memory cell comprising: a memory element situated over a silicon based substrate and which is configured to transport a current of spin polarized electrons, including: i) a first ferromagnetic layer with a first changeable magnetization state comprising iron, permalloy and/or cobalt; ii) a second ferromagnetic layer with a second non-changeable magnetization state also comprising iron, permalloy and/or cobalt and which conducts said spin current; wherein a magnitude of a spin polarized current passing through both said first ferromagnetic layer a second ferromagnetic layer can be varied to store a data value in said memory cell having at least two logic levels; a memory cell selector coupled to an output of said electron spin-based memory, said memory cell selector including a semiconductor based isolation element which can be activated to read said data value; a complementary metal oxide semiconductor (CMOS) sense amplifier coupled to said memory cell selector and which is adapted to determine said data value based on said magnitude of said current of spin polarized electrons. 17. The hybrid magnetoelectronic spin-based memory cell of claim 16, wherein said memory element is stacked on top of a second electron spin-based memory element. 18. The hybrid magnetoelectronic spin-based memory cell of claim 17, wherein said memory element and said second electron spin-based memory element share said memory cell selector. 19. The hybrid magnetoelectronic spin-based memory cell of claim 16, wherein said memory element is a three terminal, current biased device. 20. The hybrid magnetoelectronic spin-based memory cell of claim 16, including a conductive paramagnetic base layer situated between said first ferromagnetic layer and said second ferromagnetic layer, and which is adapted to create a nonequilibrium population of spin polarized electrons and an equivalent nonequilibrium magnetization M. 21. The hybrid magnetoelectronic spin-based memory cell of claim 20, wherein said nonequilibrium magnetization M in said paramagnetic conductive paramagnetic base layer base generates an electric field at an interface with said first ferromagnetic layer. 22. The hybrid magnetoelectronic spin-based memory cell of claim 16, wherein said spin polarized current has a magnitude that varies based on whether said first changeable magnetization state and said second non-changeable magnetization state are parallel or antiparallel. 23. The hybrid magnetoelectronic spin-based memory cell of claim 16, wherein said CMOS sense amplifier determines said data value by comparing an output voltage of said memory element with a reference voltage.