IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0272340
(2005-11-10)
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등록번호 |
US-7340555
(2008-03-04)
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발명자
/ 주소 |
- Ashmore,Paul Andrew
- Davies,Ian Robert
- Maine,Gene
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출원인 / 주소 |
- Dot Hill Systems Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
34 인용 특허 :
35 |
초록
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A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, bef
A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.
대표청구항
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We claim: 1. A method for performing a mirrored posted-write operation in a system having first and second redundant array of inexpensive disks (RAID) controllers in communication via a high-speed communications link, each of the RAID controllers having a CPU, a cache memory, and a bus bridge that
We claim: 1. A method for performing a mirrored posted-write operation in a system having first and second redundant array of inexpensive disks (RAID) controllers in communication via a high-speed communications link, each of the RAID controllers having a CPU, a cache memory, and a bus bridge that bridges the CPU, cache memory, and communications link, the cache memory having first and second sets of write cache buffers, and corresponding valid indicators for indicating whether each of the write cache buffers of the second set contains valid data to be flushed to a disk array by the RAID controller if the other RAID controller fails, the method comprising: receiving, by the bus bridge of the first RAID controller, data transmitted to the first RAID controller by a host computer; writing, by the bus bridge of the first RAID controller, the data to one or more of the first set of write cache buffers of the first RAID controller, in response to said bus bridge of the first RAID controller receiving the data transmitted by the host computer; broadcasting, by the bus bridge of the first RAID controller, a copy of the data to the bus bridge of the second RAID controller via the link, in response to said bus bridge of the first RAID controller receiving the data transmitted by the host computer; receiving, by the bus bridge of the second RAID controller, the copy of the data via the communications link; writing, by the bus bridge of the second RAID controller, the copy of the data to one or more of the second set of write cache buffers of the second RAID controller, in response to said receiving the copy of the data; and updating one or more of the corresponding valid indicators of the second RAID controller to indicate that said one or more of the second set of write cache buffers of the second RAID controller does not contain valid data, wherein said updating the valid indicators is performed automatically by the bus bridge of the second RAID controller in response to said receiving the copy of the data, wherein the bus bridge of the second RAID controller automatically performs the updating of the valid indicators prior to said writing the copy of the data, wherein the CPU of the second RAID controller is alleviated from updating the valid indicators because the bus bridge of the second RAID controller automatically updates the valid indicators. 2. The method of claim 1, wherein said broadcasting comprises the bus bridge of the first RAID controller transmitting to the bus bridge of the second RAID controller an address specifying a location of the one or more write cache buffers in the cache memory of the second RAID controller, wherein the bus bridge of the second RAID controller performs said automatically updating only if the address is within an address range programmed into the bus bridge of the second RAID controller by the CPU of the second RAID controller, wherein an array of cache buffers including said one or more cache buffers of the second write cache occupy said address range. 3. The method of claim 1, wherein said broadcasting by the bus bridge of the first RAID controller includes providing an indication to the bus bridge of the second RAID controller to invalidate the one or more cache buffers prior to said writing the copy of the data. 4. The method of claim 3, wherein the indication to invalidate the one or more cache buffers is comprised within a PCI-Express transaction layer packet (TLP) containing the copy of the data. 5. The method of claim 4, wherein the indication comprises a predetermined value in a predetermined address bit of the address field of the TLP header interpreted by the second bus bridge as the invalidate indication rather than as an address bit. 6. The method of claim 1, wherein said broadcasting comprises the bus bridge of the first RAID controller transmitting to the bus bridge of the second RAID controller a buffer address specifying a location of the one or more cache buffers in the cache memory of the second RAID controller, wherein said bus bridge of the second RAID controller writing the copy of the data comprises said bus bridge of the second RAID controller writing the copy of the data to the cache memory of the second RAID controller at the buffer address. 7. The method of claim 6, wherein the buffer address is specified in a PCI-Express transaction layer packet (TLP) header address field. 8. The method of claim 6, further comprising: determining, by the bus bridge of the second RAID controller, a location of one or more valid indicators of the second RAID controller for indicating whether the one or more cache buffers of the cache memory of the second RAID controller are valid, in response to said receiving the copy of the data, wherein the bus bridge of the second RAID controller determines the location based on the buffer address and a base address specifying a starting location of an array of cache buffers of the cache memory of the second RAID controller including the one or more cache buffers. 9. The method of claim 8, further comprising: storing the base address into a register of the bus bridge of the second RAID controller, prior to said receiving the copy of the data. 10. The method of claim 9, wherein said storing the base address into a register of the second bus bridge comprises the CPU of the second RAID controller storing the base address into the register during initialization of the second RAID controller. 11. The method of claim 8, wherein said bus bridge of the second RAID controller determining the location of the one or more valid indicators comprises generating an index value by subtracting the base address from the buffer address and then dividing a result of said subtracting by a predetermined size of each of the cache buffers of the array. 12. The method of claim 11, wherein said bus bridge of the second RAID controller determining the location of the one or more valid indicators further comprises multiplying the index by a predetermined size of a data structure containing the valid indicators and adding a result of said multiplying to a second base address specifying a starting location of an array of valid indicators including the one or more valid indicators. 13. The method of claim 12, further comprising: storing the second base address into a second register of the bus bridge of the second RAID controller, prior to said receiving. 14. The method of claim 13, wherein said storing the second base address into a second register of the bus bridge of the second RAID controller comprises the CPU of the second RAID controller storing the second base address into the second register during initialization of the second RAID controller. 15. The method of claim 1, wherein said broadcasting comprises the bus bridge of the first RAID controller transmitting to the bus bridge of the second RAID controller a length of the copy of the data. 16. The method of claim 1, wherein the high-speed communications link comprises a PCI-Express link. 17. The method of claim 1, wherein said bus bridge of the first RAID controller receiving data transmitted by a host computer comprises the bus bridge of the first RAID controller receiving the data from a host interface controller preceded by an address specifying a destination of the data in the cache memory of the first and second RAID controllers. 18. The method of claim 1, wherein the second RAID controller further includes one or more valid indicators for indicating whether the one or more cache buffers of the cache memory of the second RAID controller are valid, wherein said automatically updating comprises clearing the one or more valid indicators. 19. The method of claim 1, further comprising: validating, by the CPU of the second RAID controller, the one or more cache buffers, after said bus bridge of the second RAID controller writing the copy of the data. 20. The method of claim 19, further comprising: writing, by the CPU of the second RAID controller, into a directory of the second RAID controller, a logical block address of a disk array to which the copy of the data is to be written by the second RAID controller if the first RAID controller fails, prior to said second CPU validating the one or more cache buffers. 21. A bus bridge on a first redundant array of inexpensive disks (RAID) controller, the bus bridge comprising: a memory interface, coupled to a cache memory of the first RAID controller, wherein said cache memory includes a plurality of write cache buffers and a directory thereof, said directory including valid indicators for indicating whether each of said plurality of write cache buffers contains valid data to be flushed to a disk array by the first RAID controller if a second RAID controller in communication therewith fails; a first local bus interface, configured to enable a CPU of the first RAID controller to access said cache memory; a second local bus interface, for coupling the first RAID controller to said second RAID controller via a second local bus, configured to receive mirrored write-cache data broadcasted from said second RAID controller on said local bus; and control logic, coupled to said memory interface and said second local bus interface, configured to automatically control said memory interface to write said mirrored write-cache data to one of said plurality of write cache buffers, and to update said valid indicators to indicate said one of said plurality of write cache buffers does not contain valid data prior to writing said mirrored write-cache data, in response to receiving said mirrored write-cache data, wherein said CPU is alleviated from updating said valid indicators because said control logic automatically controls said memory interface to update said valid indicators. 22. The bus bridge of claim 21, wherein said second local bus comprises a PCI-Express link. 23. The bus bridge of claim 21, wherein said first local bus comprises a PCI-X bus. 24. The bus bridge of claim 21, further comprising: a first-in-first-out (FIFO) memory, coupling said memory interface and said second local bus interface, for buffering said mirrored write-cache data. 25. The bus bridge of claim 21, wherein said control logic is configured to selectively cause said memory interface to update said valid indicators. 26. The bus bridge of claim 25, wherein said second local bus interface is configured to receive said mirrored write-cache data in a transaction on said second local bus that includes an invalidate cache indicator, wherein said control logic automatically controls said memory interface to update said valid indicators only if said invalidate cache indicator indicates to update said valid indicators. 27. The bus bridge of claim 26, wherein said transaction comprises a PCI-Express memory write request transaction layer packet (TLP), wherein said control logic automatically controls said memory interface to update said valid indicators only if said TLP indicates to update said valid indicators. 28. The bus bridge of claim 27, wherein said TLP indicates to update said valid indicators if a predetermined address bit of the address field of the TLP header has a predetermined value, wherein said control logic interprets said predetermined address bit as an invalidate indicator rather than as an address bit. 29. The bus bridge of claim 25, wherein said control logic is configured to store an address range, wherein said second local bus interface is configured to receive said mirrored write-cache data in a transaction on said second local bus that includes a memory address of said one of said plurality of write cache buffers, wherein said control logic automatically controls said memory interface to update said valid indicators only if said memory address is within said address range. 30. The bus bridge of claim 21, wherein said control logic is configured to calculate an address of said valid indicators based on an address of said one of said plurality of write cache buffers. 31. The bus bridge of claim 30, wherein said address of said one of said plurality of write cache buffers is received from said second RAID controller on said local bus by said second local bus interface along with said mirrored write-cache data. 32. The bus bridge of claim 30, wherein said control logic calculating said address of said valid indicators comprises subtracting said address of said one of said plurality of write cache buffers from a base address of said plurality of write cache buffers and dividing by a predetermined size of one of said plurality of write cache buffers to generate a quotient. 33. The bus bridge of claim 32, further comprising: a register, programmable by said CPU, configured to store said base address of said plurality of write cache buffers. 34. The bus bridge of claim 32, wherein said calculating said address of said valid indicators further comprises multiplying said quotient by a predetermined size of an entry in said directory to generate a product, wherein said directory entry includes said valid indicators. 35. The bus bridge of claim 34, wherein said calculating said address of said valid indicators further comprises adding said product to a base address of said directory to generate a sum. 36. The bus bridge of claim 35, further comprising: a register, programmable by said CPU, configured to store said base address of said directory. 37. The bus bridge of claim 35, wherein said calculating said address of said valid indicators further comprises adding said sum to an offset of said valid indicators within said directory entry. 38. The bus bridge of claim 37, wherein said directory entry comprises a vector of valid bits comprising said valid indicators, wherein a first of said valid bits updated by said memory interface to indicate said one of said plurality of write cache buffers does not contain valid data is calculated by taking said address of said one of said plurality of write cache buffers modulo said predetermined size of one of said plurality of write cache buffers and then dividing by a predetermined size of a disk sector. 39. The bus bridge of claim 38, wherein a number of said valid bits updated by said memory interface to indicate said one of said plurality of write cache buffers does not contain valid data is calculated by dividing a length of said mirrored write-cache data by said predetermined size of a disk sector. 40. The bus bridge of claim 21, further comprising: a third local bus interface, for coupling to a disk interface for flushing said plurality of write cache buffers containing valid data to said disk array. 41. A system for performing a mirrored posted-write operation, comprising: two redundant array of inexpensive disks (RAID) controllers in communication via a communications link, each of said RAID controllers comprising a CPU, a write cache, and a bus bridge coupled to said CPU, said write cache, and said communications link; wherein each said bus bridge is configured to receive data transmitted to its respective RAID controller by a host computer and, in response, to write said data to its respective write cache and to broadcast a copy of said data to the other bus bridge via said link; wherein the other bus bridge is configured to, in response to receiving said copy of said data from said link, write said copy of said data to a cache buffer of its respective write cache, and to automatically invalidate said cache buffer prior to writing said copy of said data, wherein each of said respective CPUs is alleviated from invalidating said cache buffer because said bus bridge automatically invalidates said cache buffer in response to receiving said copy of said data from said link. 42. The system of claim 41, wherein each of said RAID controllers is coupled to first and second disk arrays, wherein a first of said RAID controllers is configured to control said first disk array during normal operation and a second of said RAID controllers is configured to control said second disk array during normal operation, wherein said first RAID controller write cache comprises a first portion for caching data to be written to said first disk array and said second RAID controller write cache comprises a first portion for caching data to be written to said second disk array, wherein said first RAID controller write cache comprises a second portion for caching a mirrored copy of said first portion of said second RAID controller write cache and said second RAID controller write cache comprises a second portion for caching a mirrored copy of said first portion of said first RAID controller write cache. 43. The system of claim 42, wherein each of said CPUs is configured to send a message to the other CPU to validate said cache buffer after the other bus bridge writes said copy of said data to said cache buffer. 44. The system of claim 43, wherein said message includes a logical block address of said respective disk array to which said data is to be written, wherein the other CPU writes said logical block address to said write cache prior to the other CPU validating said cache buffer. 45. The system of claim 44, wherein said message includes an identifier identifying said respective disk array to which said data is to be written, wherein the other CPU writes said identifier to said write cache prior to the other CPU validating said cache buffer. 46. The system of claim 43, wherein if said first RAID controller fails, said second RAID controller is configured to flush all valid cache buffers in said second portion of its write cache to said second disk array, wherein if said second RAID controller fails, said first RAID controller is configured to flush all valid cache buffers in said second portion of its write cache to said first disk array. 47. The system of claim 41, wherein each of said RAID controllers further comprises a host interface, coupled to said bus bridge, configured to receive said data from said host computer and to generate a transaction to said bus bridge to write said data to its respective write cache. 48. The system of claim 47, wherein said transaction comprises an address of a destination of said data in said RAID controller write cache, wherein said address also specifies said cache buffer in the other RAID controller write cache to which said copy of said data is written. 49. The system of claim 48, wherein said bus bridge broadcasts said copy of said data to the other bus bridge via said link only if said address is within an address range programmed into said bus bridge. 50. The system of claim 49, wherein if said address is within said address range programmed into said bus bridge, said bus bridge broadcasts an invalidate indicator along with said copy of said data to the other bus bridge via said link. 51. The system of claim 50, wherein said invalidate indicator comprises a predetermined value in a predetermined address bit of the address field of a PCI-Express memory write request transaction layer packet header, wherein said other bus bridge interprets said predetermined address bit as an invalidate indicator rather than as an address bit. 52. The system of claim 48, wherein the other bus bridge invalidates said cache buffer only if said address is within an address range programmed into the other bus bridge. 53. The system of claim 41, wherein said communications link comprises a PCI-Express link.
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