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A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g.,

A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.

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What is claimed is: 1. A method for optimizing hardware generated by a software-to-hardware compiler based on software source code for a program, the method comprising: identifying pointer variables in the program wherein each of the pointer variables is associated with a data width representing an

What is claimed is: 1. A method for optimizing hardware generated by a software-to-hardware compiler based on software source code for a program, the method comprising: identifying pointer variables in the program wherein each of the pointer variables is associated with a data width representing an amount of hardware resources; determining ranges of objects to which the pointer variables can possibly point during execution of the program; in response to the determining ranges of the objects, reducing the data width of at least one of the pointer variables when generating the hardware, wherein the reduced data width pointer variables are implemented such that they point to objects in the determined ranges of objects; determining whether making simultaneous reads to multiple copies of any of the reduced data width pointer variables stored on multiple memory devices would result in a net optimization; and making at least two copies of the reduced data width pointer variables across more than one memory device that were determined to result in an optimization in the analysis. 2. A method for optimizing hardware generated by a software-to-hardware compiler based on software source code for a program, the method comprising: determining ranges of values that variables in the program can possibly represent during execution of the program wherein each of the variables in the program is associated with a data width representing an amount of hardware resources; in response to the determining ranges of the values, reducing the data width of at least one of the variables when generating the hardware, wherein the hardware is configured to build and maintain reduced data width variable regions that correspond to the determined ranges of values; determining whether making simultaneous reads to multiple copies of any of the reduced data width variable regions stored on multiple memory devices would result in a net optimization; and making at least two copies of the reduced data width variable regions across more than one memory device that were determined to result in an optimization in the analysis. 3. The method of claim 2 wherein the determining ranges of values comprises determining ranges of values that variables in the program can possibly represent during execution of the program based on "assert" statements in the software source code. 4. The method of claim 2 wherein the determining ranges of values comprises determining ranges of values that variables in the program can possibly represent during execution of the program based on symbol set inference analysis. 5. A method for optimizing hardware generated by a software-to-hardware compiler based on software source code for a program, the method comprising: identifying regions instantiated in the program wherein each of the regions in the program is associated with a data width representing an amount of hardware resources; reducing the data width of at least one of the regions when using symbol set inference analysis to minimize the regions to be used by the hardware generated by the software-to-hardware compiler; determining whether making simultaneous reads to multiple copies of any of the reduced data width regions stored on multiple memory devices would result in a net optimization; and making at least two copies of the reduced data width regions across more than one memory device that were determined to result in an optimization in the analysis. 6. The method of claim 5 further comprising: dynamically performing an analysis during run-time to determine whether the making simultaneous reads to any of the reduced data width regions stored on multiple memory devices would result in a net optimization; and dynamically making during run-time the at least two copies. 7. The method of claim 5, wherein the using symbol set inference analysis comprises: generating a plurality of stacks, wherein each of the plurality of stacks is allocated a data width that minimizes hardware resources used, wherein each of the plurality of stacks is associated with one of a plurality of functions defined in the source code, and wherein each of the plurality of stacks stores function arguments, local variables, a return value, and a return address; and generating a plurality of stack pointers, wherein each of the plurality of stack pointers is associated with one of the plurality of stacks, and wherein each of the plurality of stack pointers points to the one of the plurality of stacks with which it is associated. 8. The method of claim 5 wherein the using symbol set inference analysis comprises determining ranges of values that variables in the program can possibly represent during execution of the program based on "assert" statements in the software source code. 9. The method of claim 5 wherein the using symbol set inference analysis comprises: identifying pointer variables in the program; determining ranges of objects to which the pointer variables can possibly point during execution of the program; and generating the hardware, wherein the pointer variables are implemented such that they can point only to objects in the ranges of objects. 10. The method of claim 5 wherein the using symbol set inference analysis comprises: determining ranges of values that variables in the source code can possibly represent during execution of the program; and generating the hardware, wherein the hardware is configured to build and maintain regions that correspond to only the ranges of values. 11. A programmable logic resource having hardware constructs generated by a software-to-hardware compiler based on software source code for a program, the hardware constructs configured to build and maintain regions that correspond to ranges of values associated with variables wherein each of the regions is associated with a data width representing an amount of hardware resources and to reduce the data width of at least one of the regions, wherein the ranges of values of the reduced data width regions are limited to those ranges of values that can possibly occur during execution of the program, and wherein it is determined whether making simultaneous reads to multiple copies of any of the reduced data width regions stored on multiple memory devices would result in a net optimization and making at least two copies of the reduced data width regions across more than one memory device that were determined to result in an optimization in the analysis. 12. The system of claim 11 wherein the ranges of values are based on "assert" statements in the software source code. 13. The system of claim 11 wherein the ranges of values are based on symbol set inference analysis. 14. A programmable logic resource having hardware constructs generated by a software-to-hardware compiler using symbol set inference analysis based on software source code for a program, the hardware constructs configured to use regions in memory devices to store objects corresponding to the software source code, wherein each of the regions is associated with a data width representing an amount of hardware resources and the data width of at least one of the regions is reduced, and wherein it is determined whether making simultaneous reads to multiple copies of any of the reduced data width regions stored on multiple memory devices would result in a net optimization and making at least two copies of the reduced data width regions across more than one memory device that were determined to result in an optimization in the analysis. 15. The programmable logic resource of claim 14 wherein the hardware constructs are further configured to: dynamically perform an analysis during run-time to determine whether the making simultaneous reads to any of the reduced data width regions stored on multiple memory devices regions would result in a net optimization; and dynamically make the at least two copies during run-time. 16. The programmable logic resource of claim 14, wherein the hardware constructs are further configured to: generate a plurality of stacks, wherein each of the plurality of stacks is allocated a data width that minimizes hardware resources used, wherein each of the plurality of stacks is associated with one of a plurality of functions defined in the source code, and wherein each of the plurality of stacks stores function arguments, local variables, a return value, and a return address; and generate a plurality of stack pointers, wherein each of the plurality of stack pointers is associated with one of the plurality of stacks, and wherein each of the plurality of stack pointers points to the one of the plurality of stacks with which it is associated. 17. The programmable logic resource of claim 14 wherein the hardware constructs are generated by the software-to-hardware compiler based on "assert" statements in the software source code to indicate a range of values variables can possibly represent in the program. 18. The programmable logic resource of claim 14 wherein the hardware constructs are further configured to use pointer variables that can point to objects in only ranges of objects that can be pointed to in the program. 19. The programmable logic resource of claim 14 wherein the hardware constructs are further configured to build and maintain regions that correspond to only ranges of values that objects defined in the source can possibly represent in the program.