초록 ▼

A method (100) of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (104), and forming an insulator layer on a second wafer (106). The second wafer is treated (108) to generate a structural weakness therein, and the first and second w

A method (100) of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (104), and forming an insulator layer on a second wafer (106). The second wafer is treated (108) to generate a structural weakness therein, and the first and second wafers together (110) are then bonded together so that the channels face the insulator layer. A portion of the second wafer is then removed (112) from the bonded first and second wafers at a location corresponding to the structure weakness.

대표청구항 ▼

What is claimed is: 1. A method of forming a silicon-on-insulator wafer having one or more cooling channels underlying a buried oxide layer therein, comprising: forming one or more cooling channels on a top surface of a first wafer; forming a buried oxide layer on a top surface of a second wafer; f

What is claimed is: 1. A method of forming a silicon-on-insulator wafer having one or more cooling channels underlying a buried oxide layer therein, comprising: forming one or more cooling channels on a top surface of a first wafer; forming a buried oxide layer on a top surface of a second wafer; forming a micro-bubble layer below the buried oxide layer in the second wafer, wherein a depth of the micro-bubble layer below the buried oxide layer generally corresponds to a desired depth of silicon overlying the buried oxide layer of the resulting silicon-on-insulator wafer; bonding the top surface of the first wafer to the top surface of the second wafer, wherein the one or more cooling channels abut the buried oxide layer; splitting the second wafer along the micro-bubble layer therein, resulting in a portion of the second wafer overlying the buried oxide layer, which is turn overlies the one or more channels of the first wafer; and surface treating the portion of the second wafer. 2. The method of claim 1, wherein surface treating the portion of the second wafer comprises substantially planarizing the portion of the second wafer. 3. The method of claim 1, wherein surface treating the portion of the second wafer comprises; oxidizing an exposed surface of the second wafer portion as a sacrificial oxide; and removing the sacrificial oxide. 4. The method of claim 1, wherein forming the micro-bubble layer comprises implanting the top surface of the second wafer with hydrogen ions or ions of a rare gas, wherein the implantation causes a layer of micro-bubbles to form therein at an average depth associated with an implantation energy, and wherein the average depth corresponds to the desired depth. 5. The method of claim 4, wherein splitting the second wafer comprises exposing the bonded first and second wafers to a temperature sufficient to causes micro-bubbles in the micro-bubble layer to coalesce, thereby resulting in a delamination of the second wafer portion along the micro-bubble layer. 6. The method of claim 5, wherein the temperature is about 500�� C. or greater. 7. The method of claim 1, wherein forming the buried oxide layer comprises exposing the second wafer to an oxidizing ambient. 8. A method of forming a silicon-on-insulator wafer having one or more cooling channels underlying a buried oxide layer therein, comprising: forming one or more channels on a top surface of a first wafer; forming a buried oxide layer on a top surface of a second wafer; forming a micro-bubble layer below the buried oxide layer in the second wafer, wherein a depth of the micro-bubble layer below the buried oxide layer generally corresponds to a desired depth of silicon overlying the buried oxide layer of the resulting silicon-on-insulator wafer; bonding the top surface of the first wafer to the top surface of the second wafer, wherein the one or more channels abut the buried oxide layer; splitting the second wafer along the micro-bubble layer therein, resulting in a portion of the second wafer overlying the buried oxide layer, which is turn overlies the one or more channels of the first wafer; and surface treating the portion of the second wafer, wherein surface treating the portion of the second wafer comprises; oxidizing an exposed surface of the second wafer portion as a sacrificial oxide; and removing the sacrificial oxide and wherein surface treating further comprises exposing the exposed surface wafer portion with a heat treatment in a reducing ambient after removing the sacrificial oxide.