초록 ▼

A tile used to hold one or more probes for testing a semiconductor wafer. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top

A tile used to hold one or more probes for testing a semiconductor wafer. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe tip is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinates of a bond pad on the semiconductor wafer.

대표청구항 ▼

What is claimed is: 1. In a semiconductor wafer testing system where one or more probes are used to test a semiconductor wafer, comprising: a probe platform; at least one tile attached to the probe platform and configured in a matrix having an X-axis and an orthogonal Y-axis, the tile being used to

What is claimed is: 1. In a semiconductor wafer testing system where one or more probes are used to test a semiconductor wafer, comprising: a probe platform; at least one tile attached to the probe platform and configured in a matrix having an X-axis and an orthogonal Y-axis, the tile being used to hold the one or more probes for making contacts with the semiconductor wafer, the tile comprising: one or more sites for inserting the one or more probes to test the semiconductor wafer, each site having one or more holes, each hole coupled with a slot forming an angle, the probe having a probe tip in contact with the semiconductor wafer at one end of the slot at a bottom of the tile, wherein the probe tip is aligned with X and Y coordinates of a bond pad on the semiconductor wafer. 2. The system of claim 1, wherein the angle formed by the hole and the slot is 90 degrees. 3. The system of claim 1 further comprising a view hole at each site to view the probe tip. 4. The system of claim 1, wherein each of the probes is removable from the tile without affecting remaining probes. 5. The system of claim 4, wherein each of the probes is attached to the tile with epoxy. 6. The system of claim 1, wherein each of the probes has a kink to spring the probe against a wall of the hole in tile to hold the probe in place. 7. The system of claim 1, wherein each of the probes is attached to an insulated wire. 8. The system of claim 1, wherein the probe is inserted into the tile from a top of the tile through the hole and seated on the slot. 9. A semiconductor wafer testing system having at least one probe for testing a semiconductor wafer, comprising: a probe platform; at least one tile attached to the probe platform and configured in a matrix, the tile being used to hold the at least one probe for coupling with the semiconductor wafer, the tile comprising: at least one site for inserting the at least one probe to test the semiconductor wafer, each site having at least one hole, each hole coupled with a slot forming an angle, the probe having a probe tip probing the semiconductor wafer at one end of the slot, wherein the probe tip is aligned with a bond pad on the semiconductor wafer. 10. A semiconductor wafer testing method, comprising: providing at least one probe for testing a semiconductor wafer; providing a probe platform; and attaching at least one tile to the probe platform, the at least one tile being configured in a matrix and holding the at least one probe for coupling with the semiconductor wafer, wherein the tile provides at least one site for inserting the at least one probe to test the semiconductor wafer, each site having at least one hole, each hole coupled with a slot forming an angle, the probe having a probe tip probing the semiconductor wafer at one end of the slot, wherein the probe tip is aligned with a bond pad on the semiconductor wafer.