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System and method for block-based concurrentization of software code 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
  • G06F-009/46
출원번호 US-0277504 (2002-10-22)
등록번호 US-7346902 (2008-03-18)
발명자 / 주소
  • Dutt,Bala
  • Kumar,Ajay
  • Susarla,Hanumantha R.
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Kowert,Robert C.
인용정보 피인용 횟수 : 15  인용 특허 : 35

초록

A method for inducing multi-threading in software code may use blocks of code as the basis for scheduling and to suggest concurrent execution for each block. The method may comprise marking one or more blocks of code in an application coded for sequential execution to generate marked code. The marki

대표청구항

What is claimed is: 1. A computer-implemented method, comprising: automatically marking a plurality blocks of code in an application coded for sequential execution to provide a marked code, wherein said marking comprises inserting a marker at each of the blocks to suggest that block for potential c

이 특허에 인용된 특허 (35)

  1. Kamada, Jun; Yuhara, Masanobu; Ono, Etsuo, Computer system process scheduler determining and executing processes based upon changeable priorities.
  2. Jeremiah Thomas Leo (Endwell NY) Blaner Bartholomew (Newark Valley NY), Cross-cache-line compounding algorithm for scism processors.
  3. Briggs Preston P. (Houston TX) Cooper Keith D. (Houston TX) Kennedy ; Jr. Kenneth W. (Houston TX) Torczon Linda M. (Houston TX), Digital computer register allocation and code spilling using interference graph coloring.
  4. Ishikawa Tadashi,JPX, Digital computer system capable of processing a plurality of instructions in parallel based on a VLIW architecture.
  5. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  6. Bothner Per, Java development environment using optimizing ahead-of-time compiler.
  7. Bharadwaj Jayashankar, Method and apparatus for instruction scheduling to reduce negative effects of compensation code.
  8. Greicar, Richard K., Method and apparatus for multi-part processing of program code by a single processor.
  9. Czajkowski, Grzegorz, Method and apparatus for optimized multiprocessing in a safe language.
  10. Hay, Russell C., Method and apparatus for scheduling processes based upon virtual server identifiers.
  11. Yue Kelvin K. ; Stein Daniel A. ; Sebree Michael A., Method and apparatus for sharing a time quantum.
  12. Spix George A. ; Wengelski Diane M. ; Hawkinson Stuart W. ; Johnson Mark D. ; Burke Jeremiah D. ; Thompson Keith J. ; Gaertner Gregory G. ; Brussino Giacomo G. ; Hessel Richard E. ; Barkai David M. ;, Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes.
  13. Beadle Bruce Anthony ; Brown Michael Wayne ; Paolini Michael Anthony ; Rothert Douglas Scott, Method and apparatus to selectively control processing of a method in a java virtual machine.
  14. Kranich, Uwe; Christie, David S., Method and mechanism for speculatively executing threads of instructions.
  15. Schwartz, Leon, Method for automatic parallelization of software.
  16. Cooke, Laurence H.; Phillips, Christopher E.; Wong, Dale, Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic.
  17. Stubbs David D. (Portland OR) Barnett Mark P. (Portland OR) Greenseth William A. (Portland OR), Method of generating instruction sequences for controlling data flow processes.
  18. Nguyen, Chung T., Method, system, and program for converting code to executable code using neural networks implemented in a software program.
  19. Guy E. Blelloch ; Phillip B. Gibbons ; Yossi Matias IL; Girija J. Narlikar, Methods and apparatus for scheduling parallel processors.
  20. Blelloch Guy E. ; Gibbons Phillip B. ; Matias Yossi, Methods and means for scheduling parallel processors.
  21. Charnell,William Thomas; Plummer,Wayne; Darnell,Stephen; Dias,Blaise Abel Alec; Guthrie,Philippa Joy; Kramskoy,Jeremy Paul; Sexton,Jeremy James; Wynn,Michael John; Rautenbach,Keith; Thomas,Stephen Pa, Multi-threaded fragment patching.
  22. Nemawarkar, Shashank, Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread.
  23. Schmidt,William Jon, Object oriented apparatus and method for allocating objects on an invocation stack in a dynamic compilation environment.
  24. Dangelo Carlos, Object-oriented multi-media architecture.
  25. Funaki Hiroshi (Tokyo JPX), Optimizing compiler which generates multiple instruction streams to be executed in parallel.
  26. Hirooka, Takashi; Ohta, Hiroshi; Iitsuka, Takayoshi; Kikuchi, Sumio, Parallel program generating method.
  27. Iwasawa Kyoko (Tokyo JPX) Tanaka Yoshikazu (Oomiya JPX) Gotou Shizuo (Machida JPX), Parallelization compile method and system.
  28. Zaiki Koji (Osaka JPX), Processor scheduling method for iterative loops.
  29. Tabata, Kunio; Komatsu, Hideaki, Program optimization method, and compiler using the same.
  30. McMinn Brian D. ; Gowin ; Jr. Robert D., Reorder buffer circuit accommodating special instructions operating on odd-width results.
  31. Carmean, Douglas M.; Sager, David J.; Toll, Thomas F.; Menezes, Karol F., Replay instruction morphing.
  32. Spix George A. (Eau Claire WI) Wengelski Diane M. (Eau Claire WI) Hawkinson Stuart W. (Eau Claire WI) Johnson Mark D. (Eau Claire WI) Burke Jeremiah D. (Eau Claire WI) Thompson Keith J. (Eau Claire W, System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel executi.
  33. Dutt,Bala; Kumar,Ajay; Susarla,Hanumantha R., System and method for goal-based scheduling of blocks of code for concurrent execution.
  34. Reeve Christopher L. (18 Salisbury Rd. Brookline MA 02146) Shavit Tani (One Seaborn Pl. Lexington MA 02173) Rothnie ; Jr. James B. (47 Monmouth St. Brookline MA 02146) Peters Timothy G. (11 Wilbur St, System for parallel processing that compiles a filed sequence of instructions within an iteration space.
  35. Chow, Stanley T.; Johnson, Harold J.; Gu, Yuan, Tamper resistant software-control flow encoding.

이 특허를 인용한 특허 (15)

  1. Shafi, Hazin; Adelberg, Brian; Blees, Maria; Janotti, Paulo; Sedky, Khaled, Analysis of thread synchronization events.
  2. Schloegel, Kirk; Bhatt, Devesh, Auto-generation of concurrent code for multi-core applications.
  3. Zhang, Bin; Hsu, Meichun, Coordination of tasks executed by a plurality of threads using two synchronization primitive calls.
  4. Titzer, Benjamin L.; Mathiske, Bernd J. W.; Manivannan, Karthikeyan, Efficient per-thread safepoints and local access.
  5. Lu, Jiwei Oliver; Yamada, Koichi; Beany, James D.; Shanmugavelayutham, Palaniverlrajan; Zhang, Bo, Method and apparatus for page-level monitoring.
  6. Bell, Jr., Robert H.; Capps, Jr., Louis Bennie; Paolini, Michael A.; Shapiro, Michael Jay, Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution.
  7. Papaefstathiou, Efstathios; Yu, Jinsong; Oks, Stanislav A., Protected mode scheduling of operations.
  8. Bell, Jr., Robert H.; Capps, Jr., Louis Bennie; Paolini, Michael A.; Shapiro, Michael Jay, Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict.
  9. Sanchez,Jesus; Garcia,Carlos; Madriles,Carlos; Rundberg,Peter; Marcuello,Pedro; Gonzalez,Antonio, Selection of spawning pairs for a speculative multithreaded processor.
  10. Kataoka, Masaki; Komatsu, Hideaki; Kondoh, Goh; Ohsawa, Fumitomo, Simulation method, system and program.
  11. Melski, John Eric, System and method for optimizing job scheduling within program builds.
  12. Richards, Andrew; Cook, Andrew; Riley, Colin, System and method for parallel execution of a program.
  13. Sager, David J.; Sasanka, Ruchira; Gabor, Ron; Raikin, Shlomo; Nuzman, Joseph; Peled, Leeor; Domer, Jason A.; Kim, Ho-Seop; Wu, Youfeng; Yamada, Koichi; Ngai, Tin-Fook; Chen, Howard H.; Bobba, Jayaram; Cook, Jeffery J.; Shaikh, Omar M.; Srinivas, Suresh, Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads.
  14. Bobba, Jayaram; Sasanka, Ruchira; Cook, Jeffrey J.; Das, Abhinav; Krishnaswamy, Arvind; Sager, David J.; Agron, Jason M., Using control flow data structures to direct and track instruction execution.
  15. Rice, Timothy S.; Sterland, Andrew R.; Wong, Patrick Chi Wai; Nathan, Adam D., Workflow engine for execution of web mashups.
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