Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/461
H01L-021/02
출원번호
US-0028248
(2005-01-03)
등록번호
US-7348259
(2008-03-25)
발명자
/ 주소
Cheng,Zhiyuan
Fitzgerald,Eugene A.
Antoniadis,Dimitri A.
출원인 / 주소
Massachusetts Institute of Technology
대리인 / 주소
Goodwin Procter LLP
인용정보
피인용 횟수 :
12인용 특허 :
222
초록▼
A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-sto
A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop S1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed Si1-yGey layer, strained Si1-zGez layer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.
대표청구항▼
What is claimed is: 1. A method of fabricating a semiconductor structure comprising: providing a first semiconductor substrate; forming a first structure over the first semiconductor substrate by: depositing a compositionally graded Si1-xGex buffer layer on the first semiconductor substrate, wherei
What is claimed is: 1. A method of fabricating a semiconductor structure comprising: providing a first semiconductor substrate; forming a first structure over the first semiconductor substrate by: depositing a compositionally graded Si1-xGex buffer layer on the first semiconductor substrate, wherein a Ge composition x increases to a value greater than 0.2 and a portion of the compositionally graded Si1-xGex buffer layer comprises a Ge composition greater than about 20%, and depositing one or more first material layers comprising at least one of relaxed Si1-yGey, strained Si1-zGez, strained-Si, Ge, GaAs, III-V materials, or II-VI materials, wherein Ge compositions y and z are values selected from a range of 0 to 1; bonding the first structure to a second substrate; removing the first substrate and at least a portion of the compositionally graded Si1-xGex buffer layer; removing any remaining portion of the compositionally graded Si1-xGex buffer layer, thereby exposing at least one of the one or more first material layers; and smoothing a surface of the exposed at least one of the one or more first material layers. 2. The method of claim 1, wherein the second substrate comprises an insulating layer disposed on a surface thereof. 3. The method of claim 1 further comprising forming an insulating layer over the one or more first material layers before bonding. 4. The method of claim 1 further comprising smoothing a surface of one of the one or more first material layers before bonding. 5. The method of claim 1 further comprising smoothing a surface of the first structure before bonding. 6. The method of claim 1, further comprising: after smoothing the surface of the exposed at least one of the one or more first material layers, depositing one or more second material layers over the exposed at least one of the one or more first material layers, the one or more second material layers including at least one of relaxed Si1-yGey, strained Si1-zGez, strained-Si, Ge, GaAs, III-V materials, or II-VI materials, where Ge compositions y and z are values selected from a range of 0 to 1. 7. The method of claim 1 further comprising fabricating a semiconductor device selected from the group consisting of a FET device, a MOSFET device, a MESFET device, a solar cell device, and an optoelectronic device. 8. The method of claim 1 wherein the Ge composition x increases from about 0 to a value greater than 0.2.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (222)
Lung Hsing Lan,TWX ; Lu Tao Cheng,TWX ; Wang Mam Tsung,TWX, 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate.
Bean John C. (New Providence NJ) Higashi Gregg S. (Basking Ridge NJ) Hull Robert (South Orange NJ) Peticolas Justin L. (Wescosville PA), Article comprising a lattice-mismatched semiconductor heterostructure.
Fischer Hermann,DEX ; Hofmann Franz,DEX, CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer.
Harame David L. (Mohegan Lake NY) Patton Gary L. (Poughkeepsie NY) Stork Maria C. (Yorktown Heights NY), Complementary bipolar transistor structure and method for manufacture.
Baca Albert G. (Albuquerque NM) Drummond Timothy J. (Albuquerque NM) Robertson Perry J. (Albuquerque NM) Zipperian Thomas E. (Albuquerque NM), Complementary junction heterostructure field-effect transistor.
Ismail Khaled E. (Cairo NY EGX) Stern Frank (Pleasantville NY), Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers.
Soref Richard A. (Newton Centre MA) Friedman Lionel (Holden MA), Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates.
Harari Eliyahou ; Guterman Daniel C. ; Samachisa George ; Yuan Jack H., Dual floating gate EEPROM cell array with steering gates shared adjacent cells.
Biegelsen David K. (Portola Valley CA) Sheridon Nicholas K. (Los Altos CA) Johnson Noble M. (Menlo Park CA), Fabrication of quantum confinement semiconductor light-emitting devices.
Furukawa Toshiharu ; Ellis-Monaghan John Joseph ; Slinkman James Albert, High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe.
Jack Oon Chu ; Richard Hammond ; Khalid EzzEldin Ismail ; Steven John Koester ; Patricia May Mooney ; John A. Ott, High speed composite p-channel Si/SiGe heterostructure for field effect devices.
Meyerson Bernard S. (Yorktown Heights NY), Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers.
Francois J. Henley ; Sien G. Kang ; Igor J. Malik, Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer.
Christiansen, Silke H.; Grill, Alfred; Mooney, Patricia M., Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same.
Alexander Yuri Usenko, Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon.
Dubbelday Wadad B. ; de la Houssaye Paul R. ; Kasa Shannon D. ; Lagnado Isaac, Method for making silicon germanium alloy and electric device structures.
Selvakumar Chettypalayam R. (Waterloo CAX) Chamberlain Savvas G. (Waterloo CAX), Method for making silicon-germanium devices using germanium implantation.
Hiroji Aga JP; Naoto Tate JP; Kiyoshi Mitani JP, Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method.
Fitzgerald, Eugene A., Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits.
Lynch William T. (Apex NC) Wang Kang L. (Santa Monica CA) Tanner Martin O. (Duarte CA), Method of fabricating quantum bridges by selective etching of superlattice structures.
Bin Yu ; William G. En ; Judy Xilin An ; Concetta E. Riccobene, Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer.
Gardner Mark I. ; Fulford H. Jim ; Wristers Derick J., Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication.
Yonehara, Takao; Watanabe, Kunio; Shimada, Tetsuya; Ohmi, Kazuaki; Sakaguchi, Kiyofumi, Method of manufacturing semiconductor wafer method of using and utilizing the same.
Donald F. Canaperi ; Jack Oon Chu ; Guy M. Cohen ; Lijuan Huang ; John Albrecht Ott ; Michael F. Lofaro, Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP).
Dmbkes Heinrich (Ulm DEX) Herzog Hans-J. (Neu-Ulm DEX) Jorke Helmut (Gerstetten DEX), Modulation doped field effect transistor with doped SixGe1-x-intrinsic Si layering.
Arimilli, Ravi Kumar; Fields, Jr., James Stephen; Guthrie, Guy Lynn; Joyner, Jody Bern; Lewis, Jerry Don, Multiprocessor system bus protocol with group addresses, responses, and priorities.
Canaperi, Donald F.; Chu, Jack Oon; D'Emic, Christopher P.; Huang, Lijuan; Ott, John Albrecht; Wong, Hon-Sum Philip, Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique.
Bensahel Daniel,FRX ; Campidelli Yves,FRX ; Hernandez Caroline,FRX ; Rivoire Maurice,FRX, Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively.
Bruel Michel (Veurey FRX) du Port de Poncharra Jean (St. Martin-Le-Vinoux FRX), Process for producing an insulating layer buried in a semiconductor substrate by ion implantation.
Iwasaki, Yukiko; Nishida, Shoji; Sakaguchi, Kiyofumi; Ukiyo, Noritaka, Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus.
Christiansen, Silke H.; Chu, Jack O.; Grill, Alfred; Mooney, Patricia M., Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing.
Christiansen, Silke H.; Chu, Jack O.; Grill, Alfred; Mooney, Patricia M., Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing.
Shimizu Hitoshi (Yokohama JPX) Hirayama Yoshiyuki (Yokohama JPX) Irikawa Michinori (Yokohama JPX), Schottky junction device having a Schottky junction of a semiconductor and a metal.
Kamins Theodore I. (Palo Alto) Noble David B. (Sunnyvale) Hoyt Judy L. (Palo Alto) Gibbons James F. (Palo Alto) Scott Martin P. (San Francisco CA), Selective and non-selective deposition of Si1-xGex on a Si subsrate that is partially maske.
Ozturk Mehmet C. (Cary NC) Grider Douglas T. (Raleigh NC) Sanganeria Mahesh K. (Raleigh NC) Ashburn Stanton P. (Cary NC), Selective deposition of doped silion-germanium alloy on semiconductor substrate.
Ozturk Mehmet (Cary NC) Wortman Jimmie (Chapel Hill NC) Grider Douglas (Raleigh NC), Selective germanium deposition on silicon and resulting structures.
Karl Brunner DE; Karl Eberl DE, Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates.
Wristers, Derick J.; Xiang, Qi; Buller, James F., Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer.
Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Monroe Donald P. (Berkeley Heights NJ) Silverman Paul J. (Millburn NJ) Xie Ya-Hong (Fl, Semiconductor heterostructure devices with strained semiconductor layers.
Kauffmann Bruce A. (Jericho VT) Lam Chung H. (Williston VT) Lasky Jerome B. (Essex Junction VT), Semiconductor memory cell and memory array with inversion layer.
Burghartz Joachim N. (Shrub Oak NY) Meyerson Bernard S. (Yorktown Heights NY) Sun Yuan-Chen (Katonah NY), SiGe thin film or SOI MOSFET and method for making the same.
Judy Xilin An ; Bin Yu, Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation.
An, Judy Xilin; Yu, Bin, Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation..
Chau Robert S. ; Chern Chan-Hong ; Jan Chia-Hong ; Weldon Kevin R. ; Packan Paul A. ; Yau Leopoldo D., Transistor with ultra shallow tip and method of fabrication.
Favors ; Jr. Wesley ; MacDonald Eric William ; Mukherjee Subir ; Warriner Lynn Albert, Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS.
Murari Bruno,ITX ; Villa Flavio,ITX ; Mastromatteo Ubaldo,ITX, Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication.
Kronholz, Stephan; Papageorgiou, Vassilios; Trentzsch, Martin, Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process.
Balakrishnan, Karthik; Cheng, Kangguo; Hashemi, Pouya; Reznicek, Alexander, Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.