초록 ▼

Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying m

Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

대표청구항 ▼

What is claimed is: 1. A precharge circuit, comprising: a strong precharger for precharging a selected bit line and complementary bit line during a precharge operation; and a weak precharger including an equalizing circuit for equalizing a non-selected bit line and complementary bit line during a n

What is claimed is: 1. A precharge circuit, comprising: a strong precharger for precharging a selected bit line and complementary bit line during a precharge operation; and a weak precharger including an equalizing circuit for equalizing a non-selected bit line and complementary bit line during a normal operation in which the selected bit line and complementary bit line are sensed and amplified in a memory cell array and a precharging module for precharging the selected bit line and complementary bit line during the precharge operation, wherein the equalizing circuit receives a weak equalizing signal that represents that the bit line and complementary bit line have been non-selected regardless of a row address transition; wherein the size of transistors of the weak precharger is smaller than that of transistors of the strong precharger. 2. The precharge circuit as claimed in claim 1, wherein the strong precharger includes: a first PMOS transistor connected between the bit line and a power supply voltage, the gate of the first PMOS transistor being connected to a precharge signal; a second PMOS transistor connected between the complementary bit line and the power supply voltage, the gate of the second PMOS transistor being connected to the precharge signal; and a third PMOS transistor connected between the bit line and the complementary bit line, the gate of the third PMOS transistor being connected to the precharge signal. 3. The precharge circuit as claimed in claim 1, wherein the weak precharger includes: a first PMOS transistor connected between the bit line and power supply voltage, the gate of the first PMOS transistor being connected to the precharge signal; a second PMOS transistor connected between the complementary bit line and the power supply voltage, the gate of the second PMOS transistor being connected to the precharge signal; and a third PMOS transistor connected between the bit line and the complementary bit line, the gate of the third PMOS transistor being connected to the weak equalizing signal that represents that the bit line and the complementary bit line have been non-selected. 4. The precharge circuit as claimed in claim 1, wherein the weak precharger includes: a first PMOS transistor connected between the bit line and a power supply voltage, the gate of the first PMOS transistor being connected to the precharge signal; a second PMOS transistor connected between the complementary bit line and the power supply voltage, the gate of the second PMOS transistor being connected to the precharge signal; a third PMOS transistor connected between the bit line and the complementary bit line, the gate of the third PMOS transistor being connected to the precharge signal; and a fourth PMOS transistor connected between the bit line and the complementary bit line, the gate of the fourth PMOS transistor being connected to the weak equalizing signal that represents that the bit line and the complementary bit line have been non-selected. 5. A precharge circuit, comprising: a strong precharger selected bit line and complementary bit line during a precharge operation; and a weak precharger for equalizing a non-selected bit line and complementary bit line during a normal operation selected bit line and complementary bit line during the precharge operation, wherein the weak precharger includes: a first PMOS transistor connected between the bit line and a power supply voltage, the gate of the first PMOS transistor being connected to the precharge signal; a second PMOS transistor connected between the complementary bit line and the power supply voltage, the gate of the second PMOS transistor being connected to the precharge signal; a third PMOS transistor connected between the bit line and the complementary bit line, the gate of the third PMOS transistor being connected to the precharge signal; and a fourth PMOS transistor connected between the bit line and the complementary bit line, the gate of the fourth PMOS transistor being connected to a weak equalizing signal that represents that the bit line and the complementary bit line have been non-selected regardless of a row address transition and that the non-selected bit line and complementary bit line are equalized during an operation in which a selected bit line and a complementary bit line are sensed and amplified in a memory cell array.