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The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a

The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

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What is claimed is: 1. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor wafer which has been divided into a plurality of chip regions, each having a semiconductor integrated circuit formed thereover, and has, formed over a mai

What is claimed is: 1. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor wafer which has been divided into a plurality of chip regions, each having a semiconductor integrated circuit formed thereover, and has, formed over a main surface thereof, a plurality of first electrodes to be electrically connected with the semiconductor integrated circuit; (b) providing a first card for retaining a first sheet, which has a plurality of contact terminals to be brought into contact with the first electrodes and interconnects to be electrically connected with the contact terminals, so as to cause tip portions of the contact terminals to protrude toward the main surface of the semiconductor wafer; and (c) bringing the contact terminals into contact with the first electrodes to perform an electrical test of the semiconductor integrated circuit device, wherein the tip portions of the contact terminals are disposed over a first surface of the first sheet, and a plurality of second electrodes to be electrically connected with the interconnects are disposed over a second surface which is opposite to the first surface of the first sheet, wherein the first card has a plurality of connection mechanisms to be electrically connected to the second electrodes, wherein the connection mechanisms each comprises: an elastic contact needle for pushing the second electrodes by a load generated upon contact of the contact terminals with the first electrodes; and a retainer member for retaining the contact needle and is disposed to get in touch with the second electrodes over the second surface of the first sheet, and wherein the probe needle pushes the second electrodes before the contact terminals are brought into contact with the first electrodes. 2. A fabrication method of a semiconductor integrated circuit device according to claim 1, wherein a first reinforcing member is formed in a region of the second surface of the first sheet in which at least the second electrodes are not disposed, and the semiconductor wafer and the first reinforcing member each has a first linear expansion coefficient. 3. A fabrication method of a semiconductor integrated circuit device according to claim 2, wherein the semiconductor wafer has silicon as a main component and the first reinforcing member has, as a main component, 42 alloy, silicon or a material having a linear expansion coefficient almost equal to that of silicon. 4. A fabrication method of a semiconductor integrated circuit device according to claim 1, wherein over the second surface of the first sheet, any two adjacent second electrodes are separated with a first space wider than a space between any adjacent two tip portions of the contact terminals, and the first space between any two adjacent second electrodes is set uniform. 5. A fabrication method of a semiconductor integrated circuit device according to claim 1, wherein the main surface of the semiconductor wafer is divided into a plurality of first regions, each of the chip regions is disposed in any one of the first regions, and the step (c) is performed for each of the first regions. 6. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor wafer which has been divided into a plurality of chip regions each having a semiconductor integrated circuit formed thereover, and has, formed over a main surface thereof, a plurality of first electrodes to be electrically connected with the semiconductor integrated circuit; (b) providing a first card for retaining a first sheet, which has a plurality of contact terminals to be brought into contact with the first electrodes and interconnects to be electrically connected with the contact terminals, so as to cause tip portions of the contact terminals to protrude toward the main surface of the semiconductor wafer; and (c) bringing the contact terminals into contact with the first electrodes to perform an electrical test of the semiconductor integrated circuit device, wherein the tip portions of the contact terminals are disposed over a first surface of the first sheet, and a plurality of second electrodes to be electrically connected with the interconnects are disposed over a second surface which is opposite to the first surface of the first sheet, wherein the first card has a plurality of connection mechanisms to be electrically connected to the second electrodes, wherein the connection mechanisms each comprises: an elastic contact needle for pushing the surface of the second electrodes by a load generated upon contact of the contact terminals with the first electrodes; and a retainer member for retaining the contact needle, and is disposed to get in touch with the second electrodes over the second surface of the first sheet, and wherein the surface of each of the second electrodes to be brought into contact with the contact needle has been planarized. 7. A fabrication method of a semiconductor integrated circuit device according to claim 6, wherein a first reinforcing member is formed in a region of the second surface of the first sheet in which at least the second electrodes are not disposed, and the semiconductor wafer and the first reinforcing member each has a first linear expansion coefficient. 8. A fabrication method of a semiconductor integrated circuit device according to claim 7, wherein the semiconductor wafer has silicon as a main component and the first reinforcing member has, as a main component, 42 alloy, silicon or a material having a linear expansion coefficient almost equal to that of silicon. 9. A fabrication method of a semiconductor integrated circuit device according to claim 6, wherein over the second surface of the first sheet, any two adjacent second electrodes are separated with a first space wider than a space between any adjacent two tip portions of the contact terminals, and the first space between any two adjacent second electrodes is set uniform.