Wafer bonding of thinned electronic materials and circuits to high performance substrate
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/30
H01L-021/02
H01L-021/46
출원번호
US-0164412
(2005-11-22)
등록번호
US-7358152
(2008-04-15)
발명자
/ 주소
Kub,Francis
Hobart,Karl
출원인 / 주소
The United States of America as represented by the Secretary of the Navy
대리인 / 주소
Karasek,John J.
인용정보
피인용 횟수 :
16인용 특허 :
8
초록▼
A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding
A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.
대표청구항▼
What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer
What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate by direct wafer bonding with atom-to-atom bonding; and removing the support from the front surface of the wafer; wherein the substrate has a resistivity higher than the resistivity of the wafer. 2. The method of claim 1, wherein the wafer comprises features on the front surface. 3. The method of claim 1, further comprising the step of: processing the front surface to reduce stress in the front surface, before the attaching step. 4. The method of claim 3, wherein the processing step comprises forming grooves on the front surface of the wafer. 5. The method of claim 1, further comprising the step of: applying a low stress material to the front surface, before the attaching step. 6. The method of claim 1, wherein the attaching step comprises the use of a material selected from the group consisting of a temporary adhesive, a dissolvable adhesive, an adhesive that melts, a releasable adhesive, a heat releasable adhesive, an ultraviolet releasable adhesive, a laser releasable adhesive, and a wax. 7. The method of claim 1, wherein: the wafer comprises an etch stop layer; and the thinning step comprises etching the back surface of the wafer. 8. The method of claim 1, wherein, the thinning step comprises grinding the back surface of the wafer. 9. The method of claim 7, further comprising the step of: removing the etch stop layer after the thinning step and before the bonding step. 10. The method of claim 1, wherein the thinning step comprises thinning the wafer to a thickness of about 100 μm or less. 11. The method of claim 1, further comprising the step of: reducing the surface roughness of the back surface of the wafer after the thinning step and before the bonding step. 12. The method of claim 11, wherein the step of reducing the surface roughness comprises polishing. 13. The method of claim 1, further comprising the step of: forming features on the back surface of the wafer after the thinning step and before the bonding step. 14. The method of claim 1, further comprising the step of: depositing a leakage current blocking insulator material layer onto the back surface of the wafer, the substrate, or both after the thinning step and before the bonding step. 15. The method of claim 1, further comprising the step of: depositing a metallic layer onto the thinned back surface of the wafer, the substrate, or both before the bonding step. 16. The method of claim 1, wherein the substrate has a thermal conductivity higher than the thermal conductivity of the wafer. 17. The method of claim 1, wherein the substrate has a thermal conductivity of at least about 1 W/mK. 18. The method of claim 1, further comprising the step of: cleaning the front surface of the wafer after the removing step. 19. The method of claim 1, further comprising the step of: annealing the wafer bonded to the substrate after the bonding step and before the removing step. 20. The method of claim 1, further comprising the step of: annealing the wafer bonded to the substrate after the removing step. 21. The method of claim 1, further comprising the step of: forming features on the front surface of the wafer after the removing step. 22. The method of claim 1, further comprising the step of: thinning the substrate after the bonding step. 23. The method of claim 22, wherein the step of thinning the substrate comprises thinning the substrate to a thickness of about 100 μm or less. 24. The method of claim 1, further comprising the step of: cutting the substrate and bonded wafer. 25. The method of claim 1, wherein the bonding is carried out without a bonding material.
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이 특허에 인용된 특허 (8)
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Schubert, Martin F.; Basceri, Cem; Odnoblyudov, Vladimir; Kurth, Casey; Gehrke, Thomas, Engineered substrates for semiconductor devices and associated systems and methods.
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Aksyuk, Vladimir Anatolyevich; Basavanhally, Nagesh R; Kornblit, Avinoam; Lai, Warren Yiu-Cho; Taylor, Joseph Ashley; Fullowan, Robert Francis, Process for making microelectronic element chips.
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