A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabli
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
대표청구항▼
What is claimed is: 1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is
What is claimed is: 1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and a second metallization structure over said passivation layer, wherein said second metallization structure comprises a ground plane and a signal line at a same horizontal level, wherein said signal line is separate from and enclosed by said ground plane. 2. The integrated circuit chip of claim 1, wherein said first metallization structure comprises electroplated copper. 3. The integrated circuit chip of claim 1, wherein said first metallization structure comprises aluminum. 4. The integrated circuit chip of claim 1, wherein said second metallization structure comprises electroplated copper. 5. The integrated circuit chip of claim 1, wherein said second metallization structure comprises an electroplated metal. 6. The integrated circuit chip of claim 1, wherein said second metallization structure comprises aluminum. 7. The integrated circuit chip of claim 1, wherein said second metallization structure comprises tungsten. 8. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and a second metallization structure over said passivation layer, wherein said second metallization structure comprises a ground metal and a signal line at a same horizontal level, wherein said ground metal is along both sides of said signal line and separate from said signal line. 9. The integrated circuit chip of claim 8, wherein said first metallization structure comprises electroplated copper. 10. The integrated circuit chip of claim 8, wherein said first metallization structure comprises aluminum. 11. The integrated circuit chip of claim 8, wherein said second metallization structure comprises electroplated copper. 12. The integrated circuit chip of claim 8, wherein said second metallization structure comprises an electroplated metal. 13. The integrated circuit chip of claim 8, wherein said second metallization structure comprises aluminum. 14. The integrated circuit chip of claim 8, wherein said second metallization structure comprises tungsten. 15. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and a second metallization structure over said passivation layer, wherein said second metallization structure comprises a ground plane and a contact point at a same horizontal level, wherein said contact point is separate from and enclosed by said ground plane, wherein said second metallization structure further comprises a signal interconnect passing vertically between layers through said contact point. 16. The integrated circuit chip of claim 15, wherein said first metallization structure comprises electroplated copper. 17. The integrated circuit chip of claim 15, wherein said first metallization structure comprises aluminum. 18. The integrated circuit chip of claim 15, wherein said second metallization structure comprises electroplated copper. 19. The integrated circuit chip of claim 15, wherein said second metallization structure comprises an electroplated metal. 20. The integrated circuit chip of claim 15, wherein said second metallization structure comprises aluminum. 21. The integrated circuit chip of claim 15, wherein said second metallization structure comprises tungsten.
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