IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0908346
(2005-05-09)
|
등록번호 |
US-7361993
(2008-04-22)
|
발명자
/ 주소 |
- Coolbaugh,Douglas D.
- Edelstein,Daniel C.
- Eshun,Ebenezer E.
- He,Zhong Xiang
- Rassel,Robert M.
- Stamper,Anthony K.
|
출원인 / 주소 |
- International Business Machines Corporation
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
11 인용 특허 :
6 |
초록
▼
Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal p
Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
대표청구항
▼
What is claimed is: 1. A structure, comprising: an electrically conductive wire formed in a dielectric layer on a substrate, an entire top surface of said wire coplanar with a top surface of said dielectric layer, said wire comprising a conformal and electrically conductive first liner and an elect
What is claimed is: 1. A structure, comprising: an electrically conductive wire formed in a dielectric layer on a substrate, an entire top surface of said wire coplanar with a top surface of said dielectric layer, said wire comprising a conformal and electrically conductive first liner and an electrically conductive first core conductor; a passivation layer on said top surface of said dielectric layer and said top surface of said wire, said passivation layer comprising a lower dielectric layer on said top surfaces of said dielectric layer and said wire, an intermediate dielectric layer on a top surface of said lower dielectric layer and an upper dielectric layer on a top surface of said intermediate dielectric layer; a trench in said passivation layer, said trench extending from a top surface of said passivation layer to said top surface of said wire; a conformal and electrically conductive second liner on sidewalls of said trench and in direct physical and electrical contact with said top surface of said wire; a terminal pad comprising an electrically conductive second core conductor and said second liner, said second core conductor filling all portions of said trench not filled by said second liner, a top surface of said second core conductor and surfaces of said second liner not in contact with said second core conductor or said passivation layer coplanar with a top surface of said passivation layer, a first perimeter defined by all sides of said terminal pad aligned entirely within a second perimeter defined by all sides of said wire; a ball-limiting-metallurgy pad on a top surface of said terminal pad and overlapping all sides of said terminal pad; and a solder bump on a top surface of said ball-limiting-metallurgy pad. 2. The structure of claim 1, wherein said passivation layer further includes a chemical-mechanical-polish etch stop layer formed on a top surface of said upper dielectric layer. 3. The structure of claim 1, wherein a third perimeter defined by all sides of said solder bump is aligned entirely within a fourth perimeter defined by all sides of said ball-limiting metallurgy pad. 4. The structure of claim 1, wherein said wire comprises copper and said core conductor comprises Al or AlCu alloy. 5. The structure of claim 1, wherein: said lower dielectric layer comprises silicon nitride or silicon carbide nitride; said intermediate dielectric layer comprises silicon dioxide; said upper dielectric layer comprises silicon nitride; said conductive liner comprises Ti, TiN, Ta, TaN, W or combinations thereof; and said second core conductor comprise Al or AlCu. 6. A structure, comprising: an electrically conductive wire formed in a dielectric layer on a substrate, a top surface of said wire coplanar with a top surface of said dielectric layer, said wire comprising a conformal and electrically conductive liner and an electrically conductive core conductor; a terminal pad comprising an electrically conductive layer on a top surface of an electrically conductive barrier layer, said barrier layer on said top surface of said dielectric layer and all of said top surface of said wire, a bottom surface of said barrier layer in physical and electrical contact with said wire, said top surface of said conductive layer being a top surface of said terminal pad, a bottom surface of said barrier layer being said bottom surface of said terminal pad, a first perimeter defined by all sides of said wire aligned entirely within a second perimeter defined by all sides of said terminal pad; an electrically non-conductive passivation layer on said top surface of said dielectric layer and all exposed surfaces of said terminal pad, said passivation layer comprising a lower dielectric layer on said top surface of said dielectric layer and said all exposed surfaces of said terminal pad and an intermediate dielectric layer on a top surface of said lower dielectric layer; and a via in said passivation layer, said via extending from a top surface of said passivation layer to a top surface of said terminal pad. 7. The structure of claim 6, further including a ball-limiting-metallurgy pad covering all sidewalls of said via, a region of said top surface of said terminal pad exposed in a bottom of said via and said ball-limiting-metallurgy pad extending over said top surface of said passivation layer in a region of said passivation layer surrounding said via. 8. The structure of claim 7, further including a solder bump on a top surface of said ball-limiting-metallurgy pad. 9. The structure of claim 6, wherein said wire comprises copper, said conductive barrier layer is a barrier layer to the diffusion of copper and said conductive layer comprises Al or AlCu alloy. 10. The structure of claim 6, wherein a third perimeter defined by all sidewalls of said via is aligned entirely within a fourth perimeter defined by all sides of said ball-limiting-metallurgy pad. 11. The structure of claim 6, wherein: said lower dielectric layer comprises silicon dioxide; said intermediate dielectric layer comprises silicon nitride; said conductive barrier layer comprises Ti, TiN, Ta, TaN, W or combinations thereof; and said conductive layer comprises Al or AlCu. 12. The structure of claim 6, wherein said passivation layer further includes an upper electrically non-conductive layer on a top surface of said intermediate dielectric layer, said upper layer comprising polyimide or photosensitive polyimide. 13. The structure of claim 8, wherein a third perimeter defined by all sides of said solder bump is aligned entirely within a fourth perimeter of defined by all sides of said ball-limiting-metallurgy-pad. 14. The structure of claim 1, wherein: said lower dielectric layer comprises silicon carbide nitride; said intermediate dielectric layer comprises silicon dioxide; said upper dielectric layer comprises silicon nitride; said conductive liner comprises Ti, TiN, Ta, TaN, W or combinations thereof; and said second core conductor comprises Al or AlCu.
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