Detection of tap register characteristics
IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0322919
(2005-12-30)
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등록번호 |
US-7363559
(2008-04-22)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Buckley, Maschoff & Talwalkar LLC
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인용정보 |
피인용 횟수 :
0 인용 특허 :
7 |
초록
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According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of the shifting of the first data. Next, it is determined wheth
According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of the shifting of the first data. Next, it is determined whether the second data includes the token. In some aspects, a size of the IEEE 1149.1-compliant shift register is determined based on the second data.
대표청구항
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What is claimed is: 1. A method comprising: shifting first data including a token into an IEEE 1149.1-compliant shift register; receiving second data, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of shifting the first data; determining whether the seco
What is claimed is: 1. A method comprising: shifting first data including a token into an IEEE 1149.1-compliant shift register; receiving second data, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of shifting the first data; determining whether the second data includes the token; and if the second data includes the token then, determining a size of the IEEE 1149.1-compliant shift register based on the second data, wherein determining the size comprises: identifying the token within the second data; and determining a number of bits preceding the token within the second data. 2. A method according to claim 1, wherein identifying the token within the second data comprises: identifying an inversion of the token within the second data. 3. A method according to claim 1, wherein determining whether the second data includes the token comprises: determining whether the second data includes an inversion of the token. 4. A method according to claim 1, wherein determining whether the second data includes the token comprises identifying the token within the second data, and further comprising: dividing the number of bits by a predetermined size of the IEEE 1149.1-compliant shift register to determine a number of IEEE 1149.1-compliant devices in a scan chain including the IEEE 1149.1-compliant shift register. 5. A method according to claim 1, wherein determining whether the second data includes the token comprises identifying the token within the second data, and further comprising: dividing the number of bits by a predetermined number of IEEE 1149.1-compliant devices in a scan chain including the IEEE 1149.1-compliant shift register to determine a size of the IEEE 1149.1-compliant shift register. 6. A method according to claim 1, wherein identifying the identifier within the second data comprises: identifying corruption of the identifier within the second data. 7. An apparatus comprising: a memory storing executable code; and a processor operable in conjunction with the code to: shift first data including a token into an IEEE 1149.1-compliant shift register; receive second data, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of shifting the first data; and determine whether the second data includes the token; and if the second data includes the token then, determining a size of the IEEE 1149.1-compliant shift register based on the second data, wherein determining the size comprises: identifying the token within the second data; and determining a number of bits preceding the token within the second data. 8. An apparatus according to claim 7, wherein identification of the token within the second data comprises: identification of an inversion of the token within the second data. 9. An apparatus according to claim 7, wherein determination of whether the second data includes the token comprises: determination of whether the second data includes an inversion of the token. 10. An apparatus according to claim 7, wherein determination of whether the second data includes the token comprises identification of the token within the second data, and wherein the processor is further operable in conjunction with the code to: divide the number of bits by a predetermined size of the IEEE 1149.1-compliant shift register to determine a number of IEEE 1149.1-compliant devices in a scan chain including the IEEE 1149.1-compliant shift register. 11. An apparatus according to claim 7, wherein determination of whether the second data includes the token comprises identification of the token within the second data, and wherein the processor is further operable in conjunction with the code to: divide the number of bits by a predetermined number of IEEE 1149.1-compliant devices in a scan chain including the IEEE 1149.1-compliant shift register to determine a size of the IEEE 1149.1-compliant shift register. 12. An apparatus according to claim 7, wherein identification of the identifier within the second data comprises: identification of corruption of the identifier within the second data. 13. A system comprising: a microprocessor under test including at least one IEEE 1149.1-compliant shift register; a microprocessor testing adapter coupled to the microprocessor under test; and a host system comprising: a Universal Serial Bus-compliant port coupled to the microprocessor testing adapter; a memory storing executable code; and a processor operable in conjunction with the code to: shift first data including a token into the IEEE 1149.1-compliant shift register; receive second data, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of shifting the first data; and determine whether the second data includes the token; and if the second data includes the token then, determine a size of the IEEE 1149.1-compliant shift register based on the second data, wherein determining the size comprises: identifying the token within the second data; and determining a number of bits preceding the token within the second data. 14. A system according to claim 13, wherein identification of the token within the second data comprises: identification of an inversion of the token within the second data. 15. A system according to claim 13, wherein determination of whether the second data includes the token comprises: determination of whether the second data includes an inversion of the token. 16. A system according to claim 13, wherein identification of the identifier within the second data comprises: identification of corruption of the identifier within the second data.
이 특허에 인용된 특허 (7)
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Nomura Masahiro (Tokyo JPX) Maehashi Yukio (Tokyo JPX), Coprocessor with dataflow circuitry controlling sequencing to execution unit of data received in tokens from master proc.
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Nomura Masahiro (Tokyo JPX) Maehashi Yukio (Tokyo JPX), Master processor providing tokens to dataflow processor for controlling instructions execution and data store operation.
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Liang,Bor Sung, Method and apparatus for accessing hidden data in a boundary scan test interface.
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Abdel Hafez,Khader S.; Wen,Xiaoqing; Wang,Laung Terng; Hsu,Po Ching; Kao,Shih Chia; Chao,Hao Jan; Wang,Hsin Po, Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits.
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Yamanaka, Hidekazu; Horiyama, Takashi, Self-synchronous logic circuit having test function and method of testing self-synchronous logic circuit.
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Shah Tushar (Beaverton OR), System development and debug tools for power management functions in a computer system.
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Schwendeman Robert John, Text compression transmitter and receiver.
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