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Method and apparatus for generating multiple processor-specific code segments in a single executable 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0215429 (2002-08-09)
등록번호 US-7367021 (2008-04-29)
발명자 / 주소
  • Ansari,Zia
  • Smith,Kevin B.
  • Abraham,Seth
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Schwegman, Lundberg & Woessner, P.A.
인용정보 피인용 횟수 : 13  인용 특허 : 30

초록

A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of

대표청구항

What is claimed is: 1. A method comprising: analyzing a source code segment that is to be compiled for execution by any one of a plurality of types of processors; determining whether generating a customized version of object code for the source code segment to execute on a particular one of the plu

이 특허에 인용된 특허 (30)

  1. Hodjat Babak ; Savoie Christopher J. ; Amamiya Makoto,JPX, Adaptive agent-oriented software architecture.
  2. Heninger Andrew G. (Santa Clara CA), Apparatus and method for dynamic linking of computer software components.
  3. Kimura Eiichi,JPX, Breakpoint setting/deleting system using a symbolic debugger in a digital data processing system.
  4. Chinnaswamy Ackanaickenpalayam V. (Westboro MA) Wilk Stanley A. (Worcester MA) Torrey ; Jr James H. (Grafton MA), Data processor performance advisor.
  5. Pechanek Gerald G. ; Larsen Larry D. ; Glossner Clair John ; Vassiliaadis Stamatis,NLX, Distributed processing array with component processors performing customized interpretation of instructions.
  6. Khoyi Dana (Dracut MA) Soucie Marc S. (Tyngsboro MA) Surprenant Carolyn E. (Dracut MA) Stern Laura O. (Woburn MA) Pham Ly-Huong T. (Chelmsford MA), Integration of data between typed objects by mutual, direct invocation between object managers corresponding to object t.
  7. Khoyi Dana (Dracut MA) Soucie Marc S. (Tyngsboro MA) Surprenant Carolyn E. (Dracut MA) Stern Laura O. (Woburn MA) Pham Ly-Huong T. (Chelmsford MA), Link mechanism for linking data between objects and for performing operations on the linked data in an object based syst.
  8. Radia Sanjay R. ; Lim Swee Boon ; Kessler Peter B., Mechanism for dynamically associating a service dependent representation with objects at run time.
  9. Arsenault Mark E. (Mason NH), Memory analysis system for dynamically displaying memory allocation and de-allocation events associated with an applicat.
  10. Alcorn John William, Method and apparatus for analyzing performance of a Java bean.
  11. O'Brien Stephen Caine ; Maxwell ; III Sidney R., Method and apparatus for analyzing software in a language-independent manner.
  12. Tevanian Avadis (Palo Alto CA) Demoney Michael (San Jose CA) Enderby Kevin (Redwood City CA) Wiebe Douglas (Redwood City CA) Snyder Garth (Boulder CO), Method and apparatus for architecture independent executable files.
  13. Washington Peter ; Barton Richard R., Method and apparatus for executing a family generic processor specific application.
  14. Veldhuizen Todd,CAX, Method and apparatus for generating inline code using template metaprograms.
  15. Richburg Joseph B. (Dunwoody GA), Method and apparatus for generating program code files.
  16. Kullick Steven ; Titus Diane, Method and apparatus for managing and automatically updating software programs.
  17. Johnson William C. (Los Angeles CA) McMullen Charles C. (Colorado Springs CO), Method and apparatus for re-initializing a processing device and a storage device.
  18. Smith Kevin B. ; Nelson Clark F. ; Abraham Seth, Method and apparatus for supporting multiple processor-specific code segments in a single executable.
  19. Brodersen,Robert S.; Coker,John L.; Hastings,Mark C, Method and apparatus for upgrading a software application in the presence of user modifications.
  20. Kohl Jereme, Method and system for designing, generating and storing applications.
  21. Dunn David A., Method for achieving native performance across a set of incompatible architectures using a single binary file.
  22. Carron James M. (Aiea HI) Uechi Brian K. (Honolulu HI) Khan Mohammed A. (Honolulu HI) Royston ; III Clifton W. (Honolulu HI) Abel Jay A. (Honolulu HI) Ferlane Bradley J. (Honolulu HI) Loui Robert K. , Method for operating a local terminal to execute a downloaded application program.
  23. Schwartz David C. ; Knippel Ross C., Methodand apparatus for localizing nodes in a garbage collected carded heap.
  24. Agrawal Rakesh (San Jose CA) De Michiel Linda Gail (Los Altos CA) Lindsay Bruce Gilbert (San Jose CA), Methods to support multimethod function overloading with compile-time type checking.
  25. Orimo Masayuki (Kawasaki JPX) Mori Kinji (Machida JPX) Kawano Katsumi (Kawasaki JPX) Hirasawa Shigeki (Sagamihara JPX) Fujise Hiroshi (Yokohama JPX) Suzuki Hitoshi (Owariasahi JPX) Nakamura Tomoaki (, Multiple-execution method of multiple-version programs and computer system therefor.
  26. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.
  27. Brooks Evan ; Padula Thomas J. ; Currie Robert E. ; Richert Peter A., System and method for distributing processing among one or more processors.
  28. Lloyd, Michael; Shepley, Christopher; Stidman, Sean; Browne, H. Lee; Generous, Curtis; Lycas, John, System and method for personalizing electronic mail messages.
  29. Othmer Konstantin ; Derossi Chris, System and method for remotely monitoring a plurality of computer-based systems.
  30. Ahmed Sultan, System for controlled generation of assembly language instructions using assembly language data types including instruct.

이 특허를 인용한 특허 (13)

  1. Wallach, Steven J.; Brewer, Tony, Compiler for generating an executable comprising instructions for a plurality of different instruction sets.
  2. Brewer, Tony; Wallach, Steven J., Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor.
  3. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
  4. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
  5. Wallach, Steven J.; Brewer, Tony, Microprocessor architecture having alternative memory access paths.
  6. Wallach, Steven J.; Brewer, Tony, Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set.
  7. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  8. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  9. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  10. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
  11. Lakhotia, Arun; Karim, Md. Enamul; Walenstein, Andrew, Phylogeny generation.
  12. Kamei, Mitsuhisa, Storage medium, method, and apparatus for creating a protected executable program.
  13. Brewer, Tony, Systems and methods for mapping a neighborhood of data to general registers of a processing element.
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