초록 ▼

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabli

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

대표청구항 ▼

What is claimed is: 1. A method for fabricating an integrated circuit chip comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first interconnecting structure over said first dielectric layer, wherein

What is claimed is: 1. A method for fabricating an integrated circuit chip comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first interconnecting structure over said first dielectric layer, wherein said first interconnecting structure is connected to said multiple devices, wherein said first interconnecting structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first interconnecting structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said first interconnecting structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first interconnecting structure and exposes said first contact point, and a second opening in said passivation layer is over a second contact point of said first interconnecting structure and exposes said second contact point, wherein said first and second contact points are separate from each other, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and forming a second interconnecting structure over said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second interconnecting structure, and wherein said forming said second interconnecting structure comprises a copper electroplating process. 2. The method of claim 1 further comprising forming a solder bump over said second interconnecting structure. 3. The method of claim 1, wherein said forming said second interconnecting structure comprises forming a wirebonding interconnect pad connected to said first and second contact points. 4. The method of claim 1 further comprising providing a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point and exposes said first contact point, and a fourth opening in said polymer layer is over said second contact point and exposes said second contact point, followed by said fonning said second interconnecting structure further over said polymer layer. 5. The method of claim 4, wherein said polymer layer is formed by a process comprising coating and curing. 6. The method of claim 4, wherein said polymer layer is formed by a process comprising forming a photosensitive polyimide on said passivation layer. 7. The method of claim 1, wherein said forming said second interconnecting structure further comprises a nickel forming process. 8. The method of claim 1, wherein said forming said second interconnecting structure further comprises a tungsten-containing-metal forming process. 9. The method of claim 1, wherein said forming said second interconnecting structure further comprises an aluminum sputtering process. 10. The method of claim 1, wherein said forming said second interconnecting structure further comprises a chromium forming process. 11. A method for fabricating an integrated circuit chip comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first interconnecting structure over said first dielectric layer, wherein said first interconnecting structure is connected to said multiple devices, wherein said first interconnecting structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first interconnecting structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, a passivation layer over said first interconnecting structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, and a polymer layer having a thickness greater than 2 micrometers on said passivation layer, wherein an opening in said passivation layer and in said polymer layer is over a first contact point of said first interconnecting structure and exposes said first contact point; and forming a second interconnecting structure over said first contact point and over said polymer layer, wherein said second interconnecting structure comprises an interconnect over said first contact point and over said polymer layer and a solder bump over a second contact point of said interconnect, wherein the position of said second contact point from a top perspective view is different from that of said first contact point, wherein said second contact point is connected to said first contact point, and wherein said interconnect comprises a first metal portion over said first contact point and a second metal portion over said first metal portion and over said polymer layer, wherein said solder bump is over said second metal portion, and wherein said first metal portion is formed by a first process comprising sputtering, and said second metal portion is formed by a second process comprising electroplating. 12. The method of claim 11, wherein said first process comprises sputtering aluminum. 13. The method of claim 11, wherein said second process comprises electroplating copper. 14. The method of claim 11, wherein said polymer layer is formed by a process comprising coating and curing. 15. The method of claim 11, wherein said polymer layer is formed by a process comprising forming a photosensitive polyimide on said passivation layer. 16. The method of claim 11, wherein said polymer layer is formed by a process comprising curing in nitrogen ambient. 17. A method for fabricating an integrated circuit chip comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first interconnecting structure over said first dielectric layer, wherein said first interconnecting structure is connected to said multiple devices, wherein said first interconnecting structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first interconnecting structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said first interconnecting structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, and wherein an opening in said passivation layer is over a first contact point of said first interconnecting structure and exposes said first contact point; and forming a second interconnecting structure over said first contact point and over said passivation layer, wherein said second interconnecting structure comprises an interconnect over said first contact point and over said passivation layer and a metal bump over a second contact point of said interconnect, wherein the position of said second contact point from a top perspective view is different from that of said first contact point, and wherein said second contact point is connected to said first contact point, wherein said interconnect comprises a first metal portion over said first contact point and a second metal portion over said first metal portion and over said passivation layer, wherein said metal bump is over said second metal portion, and wherein said first metal portion is formed by a first process comprising sputtering, and said second metal portion is formed by a second process comprising electroplating. 18. The method of claim 17, wherein said first process comprises sputtering aluminum. 19. The method of claim 17, wherein said second process comprises electroplating copper. 20. The method of claim 17, wherein said metal bump comprises solder.