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Methods for making integrated-circuit wiring from copper, silver, gold, and other metals

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/02
출원번호 US-0458975 (2006-07-20)
등록번호 US-7368378 (2008-05-06)
발명자 / 주소
  • Ahn,Kie Y.
  • Forbes,Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg & Woessner, P.A.
인용정보 피인용 횟수 : 7  인용 특허 : 214

초록

Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of alu

대표청구항

What is claimed: 1. A method of making integrated circuits, comprising: forming a first mask layer having one or more openings or trenches, with each opening exposing a portion of one or more transistor contact regions; forming a first conductive structure on the first mask layer, with the first co

이 특허에 인용된 특허 (214)

  1. Bruni Marie-Dominique,FRX, Anode for a flat display screen.
  2. Thomas L. Ritzdorf ; Steve L. Eudy ; Gregory J. Wilson ; Paul R. McHugh, Apparatus and method for electrochemical processing of a microelectronic workpiece, capable of modifying processing based on metrology.
  3. Chen LinLin, Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece.
  4. Chen, LinLin, Apparatus and method for electrolytically depositing a metal on a workpiece.
  5. Chen LinLin, Apparatus and method for electrolytically depositing copper on a semiconductor workpiece.
  6. Chen, Linlin; Taylor, Thomas, Apparatus and method for electrolytically depositing copper on a semiconductor workpiece.
  7. Xu Zheng ; Forster John ; Yao Tse-Yong, Apparatus for filling apertures in a film layer on a semiconductor substrate.
  8. Ritzdorf, Thomas L.; Stevens, E. Henry; Chen, LinLin; Graham, Lyndon W.; Dundas, Curt, Apparatus for low-temperature annealing of metallization microstructures in the production of a microelectronic device.
  9. Singhvi Shri ; Rengarajan Suraj ; Ding Peijun ; Yao Gongda, Barrier applications for aluminum planarization.
  10. Hichem M'Saad ; Seon Mee Cho ; Dana Tribula, Barrier layer deposition using HDP-CVD.
  11. Andricacos Panayotis Constantinou ; Datta Madhav ; Horkans Wilma Jean ; Kang Sung Kwon ; Kwietniak Keith Thomas, Barrier layers for electroplated SnPb eutectic solder joints.
  12. Reynolds Glyn J. ; Hillman Joseph T., Buffer chamber for integrating physical and chemical vapor deposition chambers together in a processing system.
  13. Lu Jiong Ping ; Hwang Ming ; Anderson Dirk N. ; Kittl Jorge A. ; Tsai Hun-Lian, CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes.
  14. Shekhar Pramanick ; Kai Yang, Chemical-mechanical polishing of semiconductors.
  15. Tada Kenichi (Hyogo JPX), Conductive layer connection structure of semiconductor device.
  16. Uzoh Cyprian E., Continuous highly conductive metal wiring structures and method for fabricating the same.
  17. Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
  18. Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
  19. Douglas Monte A. (Coppell TX), Copper dry etch process using organic and amine radicals.
  20. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
  21. Robinson Karl ; Taylor Ted, Copper electroless deposition on a titanium-containing surface.
  22. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  23. Farrar Paul A., Copper metallurgy in integrated circuits.
  24. Farrar, Paul A., Copper metallurgy in integrated circuits.
  25. Omura Masayoshi,JPX, Damascene wiring with flat surface.
  26. Zheng Bo ; Chen Ling ; Mak Alfred ; Chang Mei, Deposition of copper with increased adhesion.
  27. Hsu Chen-Chung,TWX, Dual damascene manufacturing process.
  28. Chen Liang-Yuh ; Tao Rong ; Guo Ted ; Mosely Roderick Craig, Dual damascene metallization.
  29. Chen Liang-Yuh ; Tao Rong ; Guo Ted ; Mosely Roderick Craig, Dual damascene metallization.
  30. Wetzel Jeffrey Thomas, Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation.
  31. Bin Zhao ; Liming Tsau, Dual-damascene interconnect structures and methods of fabricating same.
  32. Klein, Rita J., Electroless deposition of doped noble metals and noble metal alloys.
  33. Shacham-Diamand Yosi ; Nguyen Vinh ; Dubin Valery, Electroless deposition of metal films with spray processor.
  34. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Electroless gold plating method for forming inductor structures.
  35. Alexander S. Kozlov ; Thirumalai Palanisamy ; Dave Narasimhan, Electroless silver plating.
  36. Nguyen Tue ; Charneski Lawrence J. ; Kobayashi Masato,JPX, Enhanced CVD copper adhesion by two-step deposition process.
  37. Teong Su-Ping (Singapore SGX), Etch stop for copper damascene process.
  38. Xing Guoqiang ; Cerny Glenn A. ; Visokay Mark R., Etchstop for integrated circuits.
  39. Uchida Hiroto ; Soyama Nobuyuki ; Ogi Katsumi,JPX ; Scott Michael C.,AUX ; Cuchiaro Joseph D. ; McMillan Larry D. ; Paz de Araujo Carlos A., Ferroelectric/high dielectric constant integrated circuit and method of fabricating same.
  40. Tetsuo Matsuda JP; Hisashi Kaneko JP, Film formation method.
  41. Qing Tan ; Stanley Craig Beddingfield ; Douglas G. Mitchell, Fine pitch bumping with improved device standoff and bump volume.
  42. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper and other metals.
  43. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  44. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas ; Srikrishnan Kris Venkatraman, High aspect ratio low resistivity lines/vias by surface diffusion.
  45. Campbell Gregor (Glendale CA) Conn Robert W. (Los Angeles CA) Shoji Tatsuo (Nagoya JPX), High density plasma deposition and etching apparatus.
  46. Jin Shu ; Mu Xiao Chun ; Chen Xing ; Bourget Lawrence, High density plasma physical vapor deposition.
  47. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), High performance interconnect system for an integrated circuit.
  48. Farnworth Warren M. ; Akram Salman, IC contacts with palladium layer and flexible conductive epoxy bumps.
  49. Allen Gregory Lee (Vancouver WA), Implantation of nucleating species for selective metallization and products thereof.
  50. Farrar,Paul A., Integrated circuit and seed layers.
  51. Robert H. Havemann ; Girish A. Dixit ; Manoj Jain ; Eden Zielinski ; Qi-Zhong Hong ; Jeffrey West, Integrated circuit interconnect and method.
  52. Farrar Paul A., Integrated circuit with oxidation-resistant polymeric layer.
  53. Ting Chiu H. ; Holtkamp William H., Integrated vacuum and plating cluster system.
  54. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  55. Nakano Tadashi (Chiba JPX) Ono Hideaki (Chiba JPX), Interconnection structure for semiconductor integrated circuit and manufacture of the same.
  56. Masahiko Kobayashi JP; Hajime Sahase JP; Nobuyuki Takahashi JP, Ionization sputtering apparatus.
  57. Kobayashi Masahiko,JPX ; Takahashi Nobuyuki,JPX, Ionizing sputter device using a coil shield.
  58. Mikalesen Donald J. (Carmel NY) Rossnagel Stephen M. (White Plains NY), Large area cathode lift-off sputter deposition device.
  59. Sachdev Krishna Gandhi ; Hummel John Patrick ; Kamath Sundar Mangalore ; Lang Robert Neal ; Nendaic Anton ; Perry Charles Hampton ; Sachdev Harbans, Low TCE polyimides as improved insulator in multilayer interconnect structures.
  60. Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
  61. Jang Syun-Ming,TWX, Low dielectric constant intermetal dielectric (IMD) by formation of air gap between metal lines.
  62. Kwon Dong-chul,KRX ; Wee Young-Jin,KRX, Low resistance interconnect for a semiconductor device and method of fabricating the same.
  63. Shan Ende ; Lau Gorley ; Geha Sam, Low temperature metallization process.
  64. Keyser Thomas (Palm Bay FL) Cairns Bruce R. (Los Altos Hills CA) Anand Kranti V. (Sunnyvale CA) Petro William G. (Cupertino CA) Barry Michael L. (Palo Alto CA), Low temperature plasma nitridation process and applications of nitride films formed thereby.
  65. Farrar, Paul A., Mask on a polymer having an opening width less than that of the opening in the polymer.
  66. Gardner Donald S., Metal alloy interconnections for integrated circuits.
  67. Ahila Krishnamoorthy ; David J. Duquette ; Shyam P. Murarka, Metallization structures for microelectronic applications and process for forming the structures.
  68. Ahila Krishnamoorthy ; David J. Duquette ; Shyam P. Murarka, Metallization structures for microelectronic applications and process for forming the structures.
  69. Brors Daniel L. (Los Altos Hills CA) Fair James A. (Mountain View CA) Monnig Kenneth A. (Palo Alto CA), Method and apparatus for deposition of tungsten silicides.
  70. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  71. Farrar Paul A., Method and support structure for air bridge wiring of an integrated circuit.
  72. Omstead Thomas R. ; Wongsenakhum Panya ; Messner William J. ; Nagy Edward J. ; Starks William ; Moslehi Mehrdad M., Method and system for dispensing process gas for fabricating a device on a substrate.
  73. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
  74. Zhou Mei Sheng,SGX ; Ron-Fu Chu,SGX, Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers.
  75. Chen, Linlin; Wilson, Gregory J.; McHugh, Paul R.; Weaver, Robert A.; Ritzdorf, Thomas L., Method for electrochemically depositing metal on a semiconductor workpiece.
  76. Chen Linlin, Method for electrolytically depositing copper on a semiconductor workpiece.
  77. Svendsen Leo Gulvad (Redwood City CA) Walker Clifford James (Fremont CA) Lykins ; II James Leborn (San Jose CA), Method for electroplating a substrate containing an electroplateable pattern.
  78. Cherng Meng-Jaw,TWX ; Li Pei-Wen,TWX, Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices.
  79. Mikagi Kaoru (Tokyo JPX), Method for fabricating semiconductor device with interconnections buried in trenches.
  80. Abt Norman E. (Burlingame CA) Moazzami Reza (Oakland CA) Nissan-Cohen Yoav (Zichren Ya\akov ILX), Method for forming a ceramic oxide capacitor having barrier layers.
  81. Sundarrajan Arvind ; Saigal Dinesh, Method for forming a multilayered aluminum-comprising structure on a substrate.
  82. Matsumoto Shigeharu,JPX ; Kikuchi Kazuo,JPX, Method for forming a thin film of a metal compound by vacuum deposition.
  83. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
  84. Cooper Kent J. (Austin TX) Lin Jung-Hui (Austin TX) Roth Scott S. (Austin TX) Roman Bernard J. (Austin TX) Mazure Carlos A. (Austin TX) Nguyen Bich-Yen (Austin TX) Ray Wayne J. (Austin TX), Method for forming contact to a semiconductor device.
  85. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
  86. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Method for forming high capacitance memory cells.
  87. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
  88. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  89. Fitzsimmons John A. (Poughkeepsie NY) Havas Janos (Hopewell Junction NY) Lawson Margaret J. (Newburgh NY) Leonard Edward J. (Fishkill NY) Rhoads Bryan N. (Pine Bush NY), Method for forming patterned films on a substrate.
  90. Tsunogae Yasuo (Kawasaki JPX) Mizuno Hideharu (Kawasaki JPX) Kohara Teiji (Kawasaki JPX) Natsuume Tadao (Yokosuka JPX), Method for hydrogenation of metathesis polymers.
  91. Yang Tsung-Ju,TWX ; Wang Chien-Mei,TWX ; Kang Tsung-Kuei,TWX, Method for making intermetal dielectrics (IMD) on semiconductor integrated circuits using low dielectric constant spin-on polymers.
  92. Sekiguchi Mitsuru,JPX, Method for making semiconductor device containing low carbon film for interconnect structures.
  93. Chung Jae-Hyuk,KRX, Method for manufacturing a thin film actuated mirror having a flat light reflecting surface.
  94. Barton Carlos L. (Brooklyn CT) McGraw Robert B. (Westport CT), Method for metallizing fluoropolymer substrates.
  95. Chen Sheng-Hsiung,TWX ; Tsai Ming-Hsing,TWX, Method for preventing seed layer oxidation for high aspect gap fill.
  96. Murakami Takashi,JPX, Method for producing a semiconductor device and a semiconductor device.
  97. Fiordalice Robert ; Garcia Sam ; Ong T. P., Method of decreasing resistivity in an electrically conductive layer.
  98. van Laarhoven Josephus M. F. G. (Eindhoven NLX) de Bruin Leendert (Eindhoven NLX) van Arendonk Anton P. M. (Eindhoven NLX), Method of enabling electrical connection to a substructure forming part of an electronic device.
  99. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), Method of fabricating a high performance interconnect system for an integrated circuit.
  100. Jing-Cheng Lin TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process.
  101. Feldner Klaus, Method of fabricating integrated circuit interconnection employing tungsten/aluminum layers.
  102. Ahn Kie Y., Method of fabricating integrated circuit wiring with low RC time delay.
  103. Hsu Chen-Chung,TWX ; Chang Yih-Jau,TWX, Method of fabricating semiconductor device for preventing antenna effect.
  104. Mikagi Kaoru,JPX, Method of fabricating semiconductor device providing effective resistance against metal layer oxidation and diffusion.
  105. Wada Junichi,JPX ; Sakata Atsuko,JPX ; Katata Tomio,JPX ; Usui Takamasa,JPX ; Hasunuma Masahiko,JPX ; Shibata Hideki,JPX ; Kaneko Hisashi,JPX ; Hayasaka Nobuo,JPX ; Okumura Katsuya,JPX, Method of filling contact holes and wiring grooves of a semiconductor device.
  106. Ong Edith (Saratoga CA), Method of filling contacts in semiconductor devices.
  107. Gilton Terry L. ; Chopra Dinesh, Method of forming a metal seed layer for subsequent plating.
  108. Farrar Paul A., Method of forming a support structure for air bridge wiring of an integrated circuit.
  109. Venkatraman Ramnath ; Weitzman Elizabeth J. ; Fiordalice Robert W., Method of forming an interconnect structure.
  110. Chien Rong-Wu,TWX ; Yen Tzu-Shih,TWX, Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers.
  111. Soon-moon Jung KR; Sun-cheol Hong KR; Sang-eun Lee KR, Method of forming contact structure in a semiconductor device.
  112. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
  113. Hong Qi-Zhong ; Jeng Shin-Puu ; Hsu Wei-Yung, Method of forming diffusion barriers encapsulating copper.
  114. Choi Kyeong Keun (Ichonkun KRX), Method of forming metal interconnection layer of semiconductor device.
  115. Buynoski Matthew S. ; Lin Ming-Ren, Method of forming multiple levels of patterned metallization.
  116. Minh Van Ngo ; Shekhar Pramanick ; Takeshi Nogami, Method of forming reliable capped copper interconnects.
  117. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas, Method of making a soft metal conductor.
  118. Pan Ju-Don T. (Austin TX), Method of making an electrical multilayer interconnect.
  119. Beinglass Israel ; Srinivas Ramanujapuram A., Method of making polysilicon/tungsten silicide multilayer composite on an integrated circuit structure.
  120. Suehiro Shintaro,JPX ; Akasaka Yasushi,JPX ; Suguro Kyoichi,JPX ; Nakajima Kazuaki,JPX ; Iijima Tadashi,JPX, Method of manufacturing a semiconductor device.
  121. Nakasaki Yasushi (Yokohama JPX), Method of manufacturing a semiconductor device with a copper wiring layer.
  122. Kondo Eiichi,JPX ; Takeyasu Nobuyuki,JPX ; Ohta Tomohiro,JPX ; Kawano Yumiko,JPX ; Kaizuka Takeshi,JPX ; Jinnouchi Shinpei,JPX, Method of manufacturing semiconductor device and an apparatus for manufacturing the same.
  123. Naik Mehul ; Broydo Samuel, Method of producing an interconnect structure for an integrated circuit.
  124. Iwasaki Haruo,JPX, Method of producing cylindrical storage node of stacked capacitor in memory cell.
  125. Canaperi Donald F. (Bridgewater CT) Jagannathan Rangarajan (Patterson NY) Krishnan Mahadevaiyer (Hopewell Junction NY), Method of replenishing electroless gold plating baths.
  126. Zhou Mei Sheng,SGX ; Xu Guo-Qin,SGX ; Chan Lap, Method to deposit a platinum seed layer for use in selective copper plating.
  127. Doan Trung T. (Boise ID) Tuttle Mark E. (Boise ID), Method to form a low resistant bond pad interconnect.
  128. Mei-Sheng Zhou SG; Simon Chooi SG; Yi Xu SG, Method to form damascene interconnects with sidewall passivation to protect organic dielectrics.
  129. Uzoh Cyprian Emeka ; Greco Stephen Edward, Method to selectively fill recesses with conductive metal.
  130. Abraham Susan C., Methods and apparatus for etching semiconductor wafers.
  131. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  132. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  133. Kie Y. Ahn ; Leonard Forbes, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  134. Forbes Leonard ; Farrar Paul A. ; Ahn Kie Y., Methods and structures for silver interconnections in integrated circuits.
  135. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  136. Ahn,Kie Y.; Forbes,Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  137. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  138. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  139. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
  140. Kwon Chul-soon,KRX, Methods of fabricating copper interconnects for integrated circuits.
  141. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  142. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  143. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Microwave plasma assisted supersonic gas jet deposition of thin film materials.
  144. Lur Water (Taipei TWX) Wu Jiunn Y. (Don-Lio TWX), Multi-level conductor process in VLSI fabrication utilizing an air bridge.
  145. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
  146. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
  147. Hautala John J. ; Westendorp Johannes F. M., PECVD of TaN films from tantalum halide precursors.
  148. Chow Yu C. (Irvine CA) Liao Kuan-Yang (Irvine CA) Chin Maw-Rong (Huntington Beach CA), Plasma-nitridated self-aligned tungsten system for VLSI interconnections.
  149. Jiang Tongbi ; King Jerrold L., Plastic lead frames for semiconductor devices.
  150. Jiang Tongbi ; King Jerrold L., Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication.
  151. Stevens E. Henry ; Berner Robert W., Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece.
  152. Havemann Robert H. ; Stoltz Richard A., Process for conductors with selective deposition.
  153. Stevens, E. Henry; Pfeiffer, Richard, Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components.
  154. Misawa Nobuhiro (Kawasaki JPX), Process for fabricating integrated circuit devices.
  155. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
  156. Jain Ajay, Process for forming a semiconductor device.
  157. Tobin Philip J. ; Hegde Rama I. ; Tseng Hsing-Huang ; O'Meara David ; Wang Victor, Process for forming a semiconductor device.
  158. Matthews James A. (878 Alcosta Dr. Milpitas CA 95035), Process for forming planarized, air-bridge interconnects on a semiconductor substrate.
  159. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
  160. Hu Yongjun (Boise ID), Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium.
  161. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  162. Paul A. Farrar, Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy.
  163. Awaya Nobuyoshi (Isehara JPX) Arita Yoshinobu (Isehara JPX), Process for selectively growing thin metallic film of copper or gold.
  164. Ping-Chuan Wang ; Ronald G. Filippi ; Robert D. Edwards ; Edward W. Kiewra ; Roy C. Iggulden, Process of enclosing via for improved reliability in dual damascene interconnects.
  165. Hussein Makarem A., Process to manufacture continuous metal interconnects.
  166. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and h.
  167. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  168. Nagao Makoto (Kanagawa JPX) Akashi Goro (Kanagawa JPX), Recording medium and method of performing recording/producing on the recording medium.
  169. Hsu Wei-Yung ; Hong Qi-Zhong, Reduced temperature contact/via filling.
  170. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  171. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  172. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  173. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  174. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  175. Lemons Kyle E. (San Jose CA) Blish ; II Richard C. (Los Gatos CA) Reimer Jan D. (Palo Alto CA), Selective plasma vapor etching process.
  176. Dennison Charles H. ; Doan Trung T., Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein.
  177. Blalock Guy T. ; Howard Bradley J., Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures.
  178. Clampitt Darwin A., Semiconductor circuit interconnections and methods of making such interconnections.
  179. Rennie John,JPX ; Hatakoshi Genichi,JPX, Semiconductor device.
  180. Usami, Tatsuya, Semiconductor device and manufacturing method thereof.
  181. IIjima Tadashi,JPX ; Ono Hisako,JPX ; Ushiku Yukihiro,JPX ; Nishiyama Akira,NLX ; Nakasa Naomi,JPX, Semiconductor device and method of manufacturing the same.
  182. Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Semiconductor device having a low permittivity dielectric.
  183. Xu Zheng ; Forster John ; Yao Tse-Yong, Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches.
  184. Usami Tatsuya,JPX ; Homma Tetsuya,JPX, Semiconductor device having an organic resin layer and silicon oxide layer containing fluorine for preventing crosstalk.
  185. Amishiro Hiroyuki,JPX ; Igarashi Motoshige,JPX, Semiconductor device including a plurality of interconnection layers.
  186. Tsukune Atsuhiro (Kawasaki JPX) Suzuki Kiyokatsu (Kawasaki JPX) Matsuura Katsuyoshi (Kawasaki JPX) Mieno Fumitake (Kawasaki JPX) Yamanishi Hirokazu (Kawasaki JPX), Semiconductor device manufacturing apparatus and its cleaning method.
  187. Sugai Kazumi,JPX, Semiconductor device manufacturing method.
  188. Suehiro Shintaro,JPX ; Akasaka Yasushi,JPX ; Suguro Kyoichi,JPX ; Nakajima Kazuaki,JPX ; Iijima Tadashi,JPX, Semiconductor device wiring or electrode.
  189. Maekawa Kazuyoshi,JPX, Semiconductor device with improved connection hole for embedding an electrically conductive layer portion.
  190. Tomita, Kenichi; Inoue, Tomotoshi; Terada, Toshiyuki, Semiconductor integrated circuit device having a hollow multi-layered lead structure.
  191. Shirk Albert (Palmyra PA) Ceresa Myron (Advance NC), Sensitized polyimides and circuit elements thereof.
  192. Chittipeddi Sailesh ; Merchant Sailesh Mansinh, Silicon IC contacts using composite TiN barrier layer.
  193. Yao Gongda ; Ding Peijun ; Xu Zheng ; Kieu Hoa, Silicon-doped titanium wetting layer for aluminum plug.
  194. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Sputter deposited barrier layers.
  195. Avanzino Steven C. ; Wang Fei, Sputter-resistant hardmask for damascene trench/via formation.
  196. Chiang Tony ; Ding Peijun ; Chin Barry L., Sputtering methods for depositing stress tunable tantalum and tantalum nitride films.
  197. Kitch Vassili, Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures.
  198. Farrar, Paul A., Structures and methods to enhance copper metallization.
  199. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
  200. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  201. Konecni Anthony J. ; Bolnedi Srikanth, System and method of forming a tungstein plug.
  202. Kholodenko Arnold ; Lee Ke Ling ; Shendon Maya ; Quiles Efrain, Temperature control system for semiconductor process chamber.
  203. Cabral ; Jr. Cyril (Ossining NY) Colgan Evan G. (Suffern NY) Grill Alfred (White Plains NY), Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum.
  204. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.
  205. Hall R. Dean (Baltimore MD), Tin and gold plating process.
  206. Kaeriyama Toshiyuki,JPX, Titanium nitride metal interconnection system and method of forming the same.
  207. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
  208. Sandhu Gurtej S. (Boise ID), Tungsten silicide (WSix) deposition process for semiconductor manufacture.
  209. Isik C. Kizilyalli ; Sailesh M. Merchant ; Joseph R. Radosevich, Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability.
  210. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  211. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  212. Farnworth Warren M. ; Akram Salman, Use of palladium in IC manufacturing.
  213. Lur Water (Taipei TWX) Chen Ben (Chu-Tong TWX), VLSI device with global planarization.
  214. Wallace Robert M. ; Stoltz Richard A. ; Wilk Glen D., Zirconium and/or hafnium silicon-oxynitride gate dielectric.

이 특허를 인용한 특허 (7)

  1. Li, Baozhen; Yang, Chih-Chao, Dual damascene structure with liner.
  2. Li, Baozhen; Yang, Chih-Chao, Dual damascene structure with liner.
  3. Yang, Chih-Chao; Horak, David V.; Koburger, III, Charles W.; Ponoth, Shom, Hybrid copper interconnect structure and method of fabricating same.
  4. Yang, Chih-Chao; Horak, David V.; Koburger, III, Charles W.; Ponoth, Shom, Hybrid copper interconnect structure and method of fabricating same.
  5. Tateishi, Fuminori; Izumi, Konami; Yamaguchi, Mayumi, Manufacturing method of microstructure and microelectromechanical system.
  6. Farrar, Paul A., Structures and methods to enhance copper metallization.
  7. Farrar, Paul A., Structures and methods to enhance copper metallization.
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