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A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients

A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.

대표청구항 ▼

What is claimed is: 1. A graphics processing apparatus, comprising: an output pipeline including a plurality of memory clients; a memory controller connected to said output pipeline, said memory controller being configured to retrieve data requested by respective ones of said plurality of memory cl

What is claimed is: 1. A graphics processing apparatus, comprising: an output pipeline including a plurality of memory clients; a memory controller connected to said output pipeline, said memory controller being configured to retrieve data requested by respective ones of said plurality of memory clients from a memory; and a buffering module connected between said memory controller and said output pipeline, said buffering module including: a buffer including a buffering space shared by said plurality of memory clients; and a buffer controller connected to said buffer, said buffer controller being configured to dynamically assign portions of said buffering space to respective ones of said plurality of memory clients, said buffer controller being configured to coordinate storage of said data in said assigned portions, said buffer controller being configured to coordinate delivery of said data from said assigned portions to respective ones of said plurality of memory clients, wherein said data includes a first set of data items requested by a first memory client of said plurality of memory clients and a second set of data items requested by a second memory client of said plurality of memory clients, said buffer controller is configured to dynamically assign a first set of memory locations within said buffering space to store said first set of data items, and said buffer controller is configured to dynamically assign a second set of memory locations within said buffering space to store said second set of data items. 2. The graphics processing apparatus of claim 1, wherein said buffer controller is configured to associate said first set of data items and said second set of data items with said first memory client and said second memory client, respectively. 3. The graphics processing apparatus of claim 1, wherein said buffer controller is configured to maintain a first write pointer indicating a write memory location for said first memory client. 4. The graphics processing apparatus of claim 3, wherein said buffer controller is configured to maintain a first read pointer indicating a read memory location for said first memory client. 5. The graphics processing apparatus of claim 4, wherein said buffer controller is configured to coordinate delivery of said first set of data items to said first memory client in accordance with a First-In First-Out scheme. 6. The graphics processing apparatus of claim 4, wherein said buffer controller is configured to maintain a second write pointer indicating a write memory location for said second memory client. 7. The graphics processing apparatus of claim 6, wherein said buffer controller is configured to maintain a second read pointer indicating a read memory location for said second memory client. 8. The graphics processing apparatus of claim 7, wherein said buffer controller is configured to coordinate delivery of said second set of data items to said second memory client in accordance with a First-In First-Out scheme. 9. The graphics processing apparatus of claim 1, wherein a size of said buffering space is selected based on memory access requirements of said plurality of memory clients. 10. The graphics processing apparatus of claim 1, wherein at least one of said plurality of memory clients corresponds to an isochronous memory client. 11. A graphics processing apparatus, comprising: a unitary buffer; and a buffer controller connected to said unitary buffer, said buffer controller being configured to: assign a set of memory locations within said unitary buffer to store data requested by a first memory client; deliver said data requested by said first memory client from said set of memory locations to said first memory client; reassign said set of memory locations to store data requested by a second memory client; and deliver said data requested by said second memory client from said set of memory locations to said second memory client. 12. The graphics processing apparatus of claim 11, wherein said buffer controller is configured to maintain a first write pointer indicating a write memory location for said first memory client, and said buffer controller is configured to maintain a first read pointer indicating a read memory location for said first memory client. 13. The graphics processing apparatus of claim 12, wherein said buffer controller is configured to deliver said data requested by said first memory client in accordance with a First-In First-Out scheme. 14. The graphics processing apparatus of claim 12, wherein said buffer controller is configured to maintain a second write pointer indicating a write memory location for said second memory client, and said buffer controller is configured to maintain a second read pointer indicating a read memory location for said second memory client. 15. The graphics processing apparatus of claim 14, wherein said buffer controller is configured to deliver said data requested by said second memory client in accordance with a First-In First-Out scheme. 16. The graphics processing apparatus of claim 11, wherein said buffer controller is configured to: reassign said set of memory locations to store additional data requested by said first memory client; and deliver said additional data requested by said first memory client from said set of memory locations to said first memory client.