[특허]Rapid discrimination preambles and methods for using the same

Medtronic MiniMed, Inc.

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내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Rapid discrimination preambles and methods for using the same

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04L-007/00
미국특허분류(USC)	375/368; 370/517
출원번호	US-0027112 (2004-12-29)
등록번호	US-7369635 (2008-05-06)
발명자 / 주소	Spital,Glenn O. Morgan,Wayne A. Shahmirian,Varaz
출원인 / 주소	Medtronic MiniMed, Inc.
인용정보	피인용 횟수 : 40 인용 특허 : 26

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A system, method and program are disclosed for achieving rapid bit synchronization in low power medical device systems. Messages are transmitted via telemetry between a medical device and a communication device. The synchronization scheme uses a portion of a unique preamble bit pattern to identify the communication device allowing for economical communications with a minimum expenditure of energy. A special set of preamble bit patterns are utilized for their unique synchronization properties making them particularly suited for rapid bit synchronization....

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What is claimed is: 1. A method for achieving rapid bit synchronization in low power RF communications systems, the method comprising the steps of: attaching a preamble to a message to be delivered from a transmitting device to a receiving device, wherein the preamble is a unique bit pattern used to identify the transmitting device; receiving a portion of the preamble sent from the transmitting device; identifying a subsequence code within the portion of the preamble; accessing a lookup table to determine a bit offset value associated with the identified subsequence code, wherein the lookup table is derived from the preamble containing all subsequence codes with each subsequence code associated with a unique bit offset value and a next predicted bit value; and verifying that the next predicted bit value associated with the identified subsequence code as determined by the associated bit offset value is actually received. 2. The method of claim 1 wherein the preamble is an 8-bit pattern containing all possible combinations of 3-bit subsequences. 3. The method of claim 1 wherein the preamble is a 16-bit pattern containing all possible combinations of 4-bit subsequences. 4. The method of claim 1 wherein the preamble is a 32-bit pattern containing all possible combinations of 5-bit subsequences. 5. The method of claim 2 wherein the 8-bit pattern is 11101000. 6. The method of claim 3 wherein the 16-bit pattern is 1001101011110000. 7. The method of claim 3 wherein the 16-bit pattern is 1001111010110000. 8. The method of claim 3 wherein the 16-bit pattern is 1010011011110000. 9. The method of claim 3 wherein the 16-bit pattern is 1010011110110000. 10. The method of claim 3 wherein the 16-bit pattern is 1011001111010000. 11. The method of claim 3 wherein the 16-bit pattern is 1011010011110000. 12. The method of claim 3 wherein the 16-bit pattern is 1011110011010000. 13. The method of claim 3 wherein the 16-bit pattern is 1011110100110000. 14. The method of claim 3 wherein the 16-bit pattern is 1100110110110000. 15. The method of claim 3 wherein the 16-bit pattern is 1101001011110000. 16. The method of claim 3 wherein the 16-bit pattern is 1101011110010000. 17. The method of claim 3 wherein the 16-bit pattern is 1101111001010000. 18. The method of claim 3 wherein the 16-bit pattern is 1111001011010000. 19. The method of claim 3 wherein the 16-bit pattern is 1111010010110000. 20. The method of claim 3 wherein the 16-bit pattern is 1111010110010000. 21. The method of claim 3 wherein the 16-bit pattern is 1111011001010000. 22. A program for achieving rapid bit synchronization in a low power RF communications system, the program comprising computer usable media including at least one computer program embedded therein that causes the computer to perform the steps of: activating a listening period in a receiving device to acquire an incoming message from a transmitting device; receiving a portion of a preamble attached to the incoming message to be delivered from the transmitting device to the receiving device, wherein the preamble is a unique bit pattern used to identify the transmitting device; identifying a subsequence code within the portion of the preamble; accessing a lookup table to determine a bit offset value associated with the subsequence code, wherein the lookup table is derived from the preamble containing all subsequence codes with each subsequence code associated with a unique bit offset value and a next predicted bit value; comparing the next predicted bit value associated with the identified subsequence code to the next bit received; wherein bit synchronization is established if the next predicted bit value matches the next bit actually received; and wherein the receiver shuts down if the next predicted bit value does not match the next bit actually received. 23. The program of claim 22, wherein the preamble is an 8-bit pattern containing all possible combinations of 3-bit subsequences. 24. The program of claim 22, wherein the preamble is a 16-bit pattern containing all possible combinations of 4-bit subsequences. 25. The program of claim 22, wherein the preamble is a 32-bit pattern containing all possible combinations of 5-bit subsequences. 26. The program of claim 23, wherein the 8-bit pattern is 11101000. 27. The program of claim 24, wherein the 16-bit pattern is 1001101011110000. 28. The program of claim 24, wherein the 16-bit pattern is 1001111010110000. 29. The program of claim 24, wherein the 16-bit pattern is 1010011011110000. 30. The program of claim 24, wherein the 16-bit pattern is 1010011110110000. 31. The program of claim 24, wherein the 16-bit pattern is 1011001111010000. 32. The program of claim 24, wherein the 16-bit pattern is 1011010011110000. 33. The program of claim 24, wherein the 16-bit pattern is 1011110011010000. 34. The program of claim 24, wherein the 16-bit pattern is 1011110100110000. 35. The program of claim 24, wherein the 16-bit pattern is 1100110110110000. 36. The program of claim 24, wherein the 16-bit pattern is 1101001011110000. 37. The program of claim 24, wherein the 16-bit pattern is 1101011110010000. 38. The program of claim 24, wherein the 16-bit pattern is 1101111001010000. 39. The program of claim 24, wherein the 16-bit pattern is 1111001011010000. 40. The program of claim 24, wherein the 16-bit pattern is 1111010010110000. 41. The program of claim 24, wherein the 16-bit pattern is 1111010110010000. 42. The program of claim 24, wherein the 16-bit pattern is 1111011001010000. 43. A medical system, comprising: an ambulatory medical device (MD) comprising MD electronic control circuitry that further comprises at least one MD telemetry system and at least one MD processor that controls, at least in part, operation of the MD telemetry system and operation of the medical device, wherein the medical device is configured to provide a treatment to a body of a patient or to monitor a selected state of the body; and a communication device (CD) comprising CD electronic control circuitry that further comprises at least one CD telemetry system and at least one CD processor that controls, at least in part, operation of the CD telemetry system and operation of the communication device, wherein the CD telemetry system sends messages to or receives messages from the MD telemetry system; wherein rapid bit synchronization between the medical device and the communication device is achieved using a preamble, wherein the preamble is a unique bit pattern used to quickly identify the communication device; wherein the medical device receives a portion of the preamble from the communication device, identifies a subsequence code within the portion of the preamble, and accesses a lookup table located within the medical device to determine a bit offset value associated with the identified subsequence code; wherein the lookup table is derived from the preamble containing all subsequence codes with each subsequence code associated with a unique bit offset value and a next predicted bit value; and wherein the medical device verifies that the next predicted bit value associated with the identified subsequence code as determined by the associated bit offset value is actually received. 44. The system of claim 43 wherein the preamble is an 8-bit pattern containing all possible combinations of 3-bit subsequences. 45. The system of claim 43 wherein the preamble is a 16-bit pattern containing all possible combinations of 4-bit subsequences. 46. The system of claim 43 wherein the preamble is a 32-bit pattern containing all possible combinations of 5-bit subsequences. 47. A method for achieving rapid bit synchronization in low power RF communications systems, the method comprising the steps of: attaching a preamble to a message to be delivered from a transmitting device to a receiving device, wherein the preamble is a unique bit pattern used to quickly identify the transmitting device; preloading the preamble's unique bit pattern into a prediction register located in the receiving device prior to activation of the receiving device; activating a listening period in the receiving device to acquire the preamble from the transmitting device; receiving the preamble sent from the transmitting device, loading a portion of the received bits of the preamble into a shift register located in the receiving device; predicting the value of the current bit, wherein the portion of the previously received bits are used to predict the value of the current bit using a lookup table, wherein the lookup table includes a multiplexer coupled to the prediction register, and wherein the multiplexer selects the appropriate value of the current bit from the prediction register; and comparing the predicted value of the current received bit to the actual value of the current received bit using an XOR gate, wherein the XOR gate produces a preamble error out signal, and wherein the error out signal inputs into a signal acquisition/rejection module which declares signal acquisition or signal rejection based on predefined acquisition/rejection criteria. 48. The method of claim 47, wherein the predefined acquisition/rejection criteria is a single bit error. 49. The method of claim 47, wherein the predefined acquisition/rejection criteria is a multiple bit error.

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